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Age
*
changed file() to open() in python scripts
Clifford Wolf
2015-05-11
*
Added "pmuxtree" command
Clifford Wolf
2015-04-07
*
fix for python 2.6.6
Clifford Wolf
2015-03-20
*
Various fixes for memories with offsets
Clifford Wolf
2015-02-14
*
Added $meminit support to "memory" command
Clifford Wolf
2015-02-14
*
Added $meminit test case
Clifford Wolf
2015-02-14
*
Some test related fixes
Clifford Wolf
2015-02-12
*
Bugfix in resource sharing test
Clifford Wolf
2015-01-27
*
Refactoring of memory_bram and xilinx brams
Clifford Wolf
2015-01-18
*
improvements in muxtree/select_leaves test
Clifford Wolf
2015-01-18
*
Improvements in opt_muxtree
Clifford Wolf
2015-01-18
*
Tiny fix in vcdcd.pl
Clifford Wolf
2015-01-13
*
Added memory_bram "shuffle_enable" feature
Clifford Wolf
2015-01-04
*
Added "memory -bram"
Clifford Wolf
2015-01-03
*
Added memory_bram 'or_next_if_better' feature
Clifford Wolf
2015-01-03
*
memory_bram transp support
Clifford Wolf
2015-01-03
*
Progress in memory_bram
Clifford Wolf
2015-01-03
*
Added proper clkpol support to memory_bram
Clifford Wolf
2015-01-02
*
Fixes and improvements in bram test
Clifford Wolf
2015-01-02
*
Progress in bram testbench
Clifford Wolf
2015-01-02
*
Progress in memory_bram
Clifford Wolf
2015-01-02
*
Progress in memory_bram
Clifford Wolf
2015-01-02
*
Progress in bram testbench
Clifford Wolf
2015-01-01
*
Bram testbench (incomplete)
Clifford Wolf
2015-01-01
*
Added "yosys -qq" to also quiet warning messages
Clifford Wolf
2014-11-09
*
Added support for task and function args in parentheses
Clifford Wolf
2014-10-27
*
Added "synth" command
Clifford Wolf
2014-09-14
*
Fixed autotest for non-basename arguments
Clifford Wolf
2014-09-06
*
Added tests/various/constmsk_test.ys
Clifford Wolf
2014-09-04
*
Added autotest -e (do not use -noexpr on write_verilog)
Clifford Wolf
2014-08-30
*
Cosmetic changes to FSM tests
Clifford Wolf
2014-08-21
*
Some improvements in FSM mapping and recoding
Clifford Wolf
2014-08-14
*
Added test_verific mode to tests/fsm/generate.py
Clifford Wolf
2014-08-12
*
Added multi-dim memory test (requires iverilog git head)
Clifford Wolf
2014-08-12
*
Fixed FSM mapping for multiple reset-like signals
Clifford Wolf
2014-08-10
*
Some improvements in fsm_opt and fsm_map for FSM with unreachable states
Clifford Wolf
2014-08-09
*
Improved FSM tests
Clifford Wolf
2014-08-08
*
Added FSM test bench
Clifford Wolf
2014-08-08
*
Improved scope resolution of local regs in Verilog+AST frontend
Clifford Wolf
2014-08-05
*
Fixed AST handling of variables declared inside a functions main block
Clifford Wolf
2014-08-05
*
Added "wreduce" to some of the standard test benches
Clifford Wolf
2014-08-03
*
Consolidated hana test benches into fewer files
Clifford Wolf
2014-08-01
*
Added "test_autotb -n <num_iter>" option
Clifford Wolf
2014-08-01
*
Added "make -j{N}" support to "make test"
Clifford Wolf
2014-07-30
*
Renamed "write_autotest" to "test_autotb" and moved to passes/tests/
Clifford Wolf
2014-07-29
*
Added support for "upto" wires to Verilog front- and back-end
Clifford Wolf
2014-07-28
*
Improvements in tests/vloghtb
Clifford Wolf
2014-07-28
*
Added techmap -extern
Clifford Wolf
2014-07-27
*
Added tests/various/.gitignore
Clifford Wolf
2014-07-26
*
Added tests/various/submod_extract.ys
Clifford Wolf
2014-07-26
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