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* Major redesign of expr width/sign detecion (verilog/ast frontend)Clifford Wolf2013-07-09
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* Fixed another bug found using vloghammerClifford Wolf2013-07-07
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* Removed tests/xsthammerClifford Wolf2013-07-07
| | | | | This test is now available as 'vloghammer' in a seperate repository: https://github.com/cliffordwolf/VlogHammer
* Fixed vivado related xsthammer bugsClifford Wolf2013-07-05
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* Various improvements in xsthammer report generatorClifford Wolf2013-07-05
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* Added work-around to isim bug in xsthammer report scriptClifford Wolf2013-07-05
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* Added CARRY4 Xilinx cell to xsthammer cell libClifford Wolf2013-07-05
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* Added xsthammer report generatorClifford Wolf2013-07-05
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* Improved xsthammer quartus supportClifford Wolf2013-07-04
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* Added Altera Cyclon III cell library to xsthammerClifford Wolf2013-07-04
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* Added defparam support to Verilog/AST frontendClifford Wolf2013-07-04
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* Added Altera Quartus support to xsthammerClifford Wolf2013-07-03
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* Progress in xsthammerClifford Wolf2013-07-03
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* Added vivado support to xsthammerClifford Wolf2013-06-26
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* Added timout functionality to SAT solverClifford Wolf2013-06-20
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* Added "eval" passClifford Wolf2013-06-19
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* Added more stuff to xsthammer, found first xst bugClifford Wolf2013-06-17
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* Added ternary op and concat op to xsthammerClifford Wolf2013-06-15
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* Added consteval testing to xsthammer and fixed bugsClifford Wolf2013-06-13
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* More xsthammer improvements (using xst 14.5 now)Clifford Wolf2013-06-13
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* Another fix for a bug found using xsthammerClifford Wolf2013-06-12
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* Further improved and extended xsthammerClifford Wolf2013-06-11
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* More xsthammer improvementsClifford Wolf2013-06-10
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* Progress xsthammer scriptsClifford Wolf2013-06-10
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* Progress in xsthammer: working proof for cell modelsClifford Wolf2013-06-10
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* Progress on xsthammerClifford Wolf2013-06-10
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* Added first xsthammer scriptsClifford Wolf2013-06-10
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* Fixed undef behavior in tests/asicworld/code_verilog_tutorial_fsm_full_tb.vClifford Wolf2013-05-24
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* Removed test cases that have been moved to yosys-test.Clifford Wolf2013-05-17
| | | | https://github.com/cliffordwolf/yosys-tests/
* Improved vcdcd.pl (added -d option)Clifford Wolf2013-05-14
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* Some improvements in vcdcd.plClifford Wolf2013-05-14
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* Fixed a bug in AST frontend for cases with non-blocking assigned variables ↵Clifford Wolf2013-04-13
| | | | as case values
* Now only use value from "initial" when no matching "always" block is foundClifford Wolf2013-03-31
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* Added test cases from 2012 paper on comparison of foss verilog synthesis toolsClifford Wolf2013-03-31
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* Added k68 (m68k compatible cpu) test case from verilatorClifford Wolf2013-03-31
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* Renamed hansimem.v test case to mem_arst.vClifford Wolf2013-03-24
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* Added hansimem testcase (memory with async reset)Clifford Wolf2013-03-24
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* Set execute bit on tests/openmsp430/run-synth.sh for realClifford Wolf2013-03-17
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* set executable flags to run-synth.sh, added .gitignoreJohann Glaser2013-03-17
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* added ckeck for Icarus Verilog, otherwise the tests are silently stoppedJohann Glaser2013-03-17
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* added more .gitignore files (make test)Clifford Wolf2013-01-05
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* initial importClifford Wolf2013-01-05