yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Added "make -j{N}" support to "make test"	Clifford Wolf	2014-07-30
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*	Renamed "write_autotest" to "test_autotb" and moved to passes/tests/	Clifford Wolf	2014-07-29
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*	Added support for "upto" wires to Verilog front- and back-end	Clifford Wolf	2014-07-28
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*	Improvements in tests/vloghtb	Clifford Wolf	2014-07-28
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*	Added techmap -extern	Clifford Wolf	2014-07-27
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*	Added tests/various/.gitignore	Clifford Wolf	2014-07-26
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*	Added tests/various/submod_extract.ys	Clifford Wolf	2014-07-26
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*	Use "wget -N" in tests/vloghtb/run-test.sh	Clifford Wolf	2014-07-26
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*	Renamed some of the test cases in tests/simple to avoid name collisions	Clifford Wolf	2014-07-25
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*	Use "opt -fine" in test/vloght/test_mapopt.sh	Clifford Wolf	2014-07-21
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*	Added "opt_const -fine" and "opt_reduce -fine"	Clifford Wolf	2014-07-21
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*	Various improvements in test/vloghtb	Clifford Wolf	2014-07-21
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*	Wider range of cell types supported in "share" pass	Clifford Wolf	2014-07-21
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*	Added yet another resource sharing test case	Clifford Wolf	2014-07-20
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*	Supercell creation for $div/$mod worked all along, fixed test benches	Clifford Wolf	2014-07-20
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*	Improved tests/share/generate.py	Clifford Wolf	2014-07-20
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*	Small fix in tests/vloghtb/run-test.sh	Clifford Wolf	2014-07-20
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*	Added "miter -equiv -flatten"	Clifford Wolf	2014-07-20
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*	Added tests/vloghtb/test_share.sh	Clifford Wolf	2014-07-20
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*	Added tests/share for testing "share" supercell creation	Clifford Wolf	2014-07-20
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*	Added tests/vloghtb	Clifford Wolf	2014-07-20
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*	Added SAT-based write-port sharing to memory_share	Clifford Wolf	2014-07-19
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*	Fixed bug in memory_share feedback-to-en code	Clifford Wolf	2014-07-19
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*	Added translation from read-feedback to en-signals in memory_share	Clifford Wolf	2014-07-18
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*	Bugfix in tests/memories/run-test.sh	Clifford Wolf	2014-07-18
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*	added tests/memories	Clifford Wolf	2014-07-18
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*	Also simulate unmapped memories in "make test"	Clifford Wolf	2014-07-17
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*	Implemented dynamic bit-/part-select for memory writes	Clifford Wolf	2014-07-17
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*	Added support for bit/part select to mem2reg rewriter	Clifford Wolf	2014-07-17
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*	Added support for constant bit- or part-select for memory writes	Clifford Wolf	2014-07-17
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*	Changed tests/techmap/mem_simple_4x1_map for new $mem/$memwr WR_EN interface	Clifford Wolf	2014-07-16
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*	Added note to "make test": use git checkout of iverilog	Clifford Wolf	2014-07-16
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*	now ignore init attributes on non-register wires in sat command	Clifford Wolf	2014-07-05
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*	fixed parsing of constant with comment between size and value	Clifford Wolf	2014-07-02
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*	Fixed handling of mixed real/int ternary expressions	Clifford Wolf	2014-06-25
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*	Little steps in realmath test bench	Clifford Wolf	2014-06-21
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*	Added test case for AstNode::MEM2REG_FL_CMPLX_LHS	Clifford Wolf	2014-06-17
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*	Improved handling of relational op of real values	Clifford Wolf	2014-06-17
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*	Little steps in realmath test bench	Clifford Wolf	2014-06-16
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*	Removed long running tests from tests/simple/realexpr.v (replaced by ↵	Clifford Wolf	2014-06-15
\| \| \| \|	tests/realmath)
*	Added tests/realmath to "make test"	Clifford Wolf	2014-06-15
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*	Improved realmath test bench	Clifford Wolf	2014-06-15
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*	improved realmath test bench	Clifford Wolf	2014-06-14
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*	progress in realmath test bench	Clifford Wolf	2014-06-14
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*	added first draft of real math testcase generator	Clifford Wolf	2014-06-14
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*	Added support for math functions	Clifford Wolf	2014-06-14
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*	Added realexpr.v test case	Clifford Wolf	2014-06-14
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*	Added read_verilog -sv options, added support for bit, logic,	Clifford Wolf	2014-06-12
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*	added tests for new verilog features	Clifford Wolf	2014-06-07
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*	Added tests/simple/repwhile.v	Clifford Wolf	2014-06-06
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