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Commit message (Expand)AuthorAge
* Fixed parsing of default cases when not last caseClifford Wolf2013-11-18
* Fixed handling of power operatorClifford Wolf2013-11-07
* Behavior should be identical now to rev. 0b4a64ac6adbd6 (next: testing before...Clifford Wolf2013-11-02
* Various ast changes for early expression width detection (prep for constfold ...Clifford Wolf2013-11-02
* Added support for complex set-reset flip-flops in proc_dffClifford Wolf2013-10-24
* Improved handling of dff with async resetsClifford Wolf2013-10-21
* Moved common techlib files to techlibs/commonClifford Wolf2013-09-15
* Added support for "2**n" shifter encodingClifford Wolf2013-08-12
* Added $div and $mod technology mappingClifford Wolf2013-08-09
* More fixes in ternary op sign handlingClifford Wolf2013-07-12
* Fixed sign handling in ternary operatorClifford Wolf2013-07-12
* Another vloghammer related bugfixClifford Wolf2013-07-11
* More fixes in ast expression sign/width handlingClifford Wolf2013-07-09
* Merge branch 'master' of Wolf2013-07-09
| * Major redesign of expr width/sign detecion (verilog/ast frontend)Clifford Wolf2013-07-09
* | Fixed shift ops with large right hand sideClifford Wolf2013-07-09
* Fixed another bug found using vloghammerClifford Wolf2013-07-07
* Removed tests/xsthammerClifford Wolf2013-07-07
* Fixed vivado related xsthammer bugsClifford Wolf2013-07-05
* Various improvements in xsthammer report generatorClifford Wolf2013-07-05
* Added work-around to isim bug in xsthammer report scriptClifford Wolf2013-07-05
* Added CARRY4 Xilinx cell to xsthammer cell libClifford Wolf2013-07-05
* Added xsthammer report generatorClifford Wolf2013-07-05
* Improved xsthammer quartus supportClifford Wolf2013-07-04
* Added Altera Cyclon III cell library to xsthammerClifford Wolf2013-07-04
* Added defparam support to Verilog/AST frontendClifford Wolf2013-07-04
* Added Altera Quartus support to xsthammerClifford Wolf2013-07-03
* Progress in xsthammerClifford Wolf2013-07-03
* Added vivado support to xsthammerClifford Wolf2013-06-26
* Added timout functionality to SAT solverClifford Wolf2013-06-20
* Added "eval" passClifford Wolf2013-06-19
* Added more stuff to xsthammer, found first xst bugClifford Wolf2013-06-17
* Added ternary op and concat op to xsthammerClifford Wolf2013-06-15
* Added consteval testing to xsthammer and fixed bugsClifford Wolf2013-06-13
* More xsthammer improvements (using xst 14.5 now)Clifford Wolf2013-06-13
* Another fix for a bug found using xsthammerClifford Wolf2013-06-12
* Further improved and extended xsthammerClifford Wolf2013-06-11
* More xsthammer improvementsClifford Wolf2013-06-10
* Progress xsthammer scriptsClifford Wolf2013-06-10
* Progress in xsthammer: working proof for cell modelsClifford Wolf2013-06-10
* Progress on xsthammerClifford Wolf2013-06-10
* Added first xsthammer scriptsClifford Wolf2013-06-10
* Fixed undef behavior in tests/asicworld/code_verilog_tutorial_fsm_full_tb.vClifford Wolf2013-05-24
* Removed test cases that have been moved to yosys-test.Clifford Wolf2013-05-17
* Improved (added -d option)Clifford Wolf2013-05-14
* Some improvements in vcdcd.plClifford Wolf2013-05-14
* Fixed a bug in AST frontend for cases with non-blocking assigned variables as...Clifford Wolf2013-04-13
* Now only use value from "initial" when no matching "always" block is foundClifford Wolf2013-03-31
* Added test cases from 2012 paper on comparison of foss verilog synthesis toolsClifford Wolf2013-03-31
* Added k68 (m68k compatible cpu) test case from verilatorClifford Wolf2013-03-31