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* Added tests/vloghtb/test_share.shClifford Wolf2014-07-20
* Added tests/share for testing "share" supercell creationClifford Wolf2014-07-20
* Added tests/vloghtbClifford Wolf2014-07-20
* Added SAT-based write-port sharing to memory_shareClifford Wolf2014-07-19
* Fixed bug in memory_share feedback-to-en codeClifford Wolf2014-07-19
* Added translation from read-feedback to en-signals in memory_shareClifford Wolf2014-07-18
* Bugfix in tests/memories/run-test.shClifford Wolf2014-07-18
* added tests/memoriesClifford Wolf2014-07-18
* Also simulate unmapped memories in "make test"Clifford Wolf2014-07-17
* Implemented dynamic bit-/part-select for memory writesClifford Wolf2014-07-17
* Added support for bit/part select to mem2reg rewriterClifford Wolf2014-07-17
* Added support for constant bit- or part-select for memory writesClifford Wolf2014-07-17
* Changed tests/techmap/mem_simple_4x1_map for new $mem/$memwr WR_EN interfaceClifford Wolf2014-07-16
* Added note to "make test": use git checkout of iverilogClifford Wolf2014-07-16
* now ignore init attributes on non-register wires in sat commandClifford Wolf2014-07-05
* fixed parsing of constant with comment between size and valueClifford Wolf2014-07-02
* Fixed handling of mixed real/int ternary expressionsClifford Wolf2014-06-25
* Little steps in realmath test benchClifford Wolf2014-06-21
* Added test case for AstNode::MEM2REG_FL_CMPLX_LHSClifford Wolf2014-06-17
* Improved handling of relational op of real valuesClifford Wolf2014-06-17
* Little steps in realmath test benchClifford Wolf2014-06-16
* Removed long running tests from tests/simple/realexpr.v (replaced by tests/re...Clifford Wolf2014-06-15
* Added tests/realmath to "make test"Clifford Wolf2014-06-15
* Improved realmath test benchClifford Wolf2014-06-15
* improved realmath test benchClifford Wolf2014-06-14
* progress in realmath test benchClifford Wolf2014-06-14
* added first draft of real math testcase generatorClifford Wolf2014-06-14
* Added support for math functionsClifford Wolf2014-06-14
* Added realexpr.v test caseClifford Wolf2014-06-14
* Added read_verilog -sv options, added support for bit, logic,Clifford Wolf2014-06-12
* added tests for new verilog featuresClifford Wolf2014-06-07
* Added tests/simple/repwhile.vClifford Wolf2014-06-06
* Progress in Verific bindingsClifford Wolf2014-03-17
* Progress in Verific bindingsClifford Wolf2014-03-14
* Fixed yosys path in tests/techmap/mem_simple_4x1_runtest.shClifford Wolf2014-03-11
* Use "verilog -noattr" in tests/techmap/mem_simple_4x1 test (for old iverilog)Clifford Wolf2014-03-11
* Use private namespace in mem_simple_4x1_mapClifford Wolf2014-02-21
* Added tests/techmap/mem_simple_4x1Clifford Wolf2014-02-21
* Added vcd2txt.pl and txt2tikztiming.py (tests/tools/...)Clifford Wolf2014-02-19
* Added frontend (-f) option to autotest.shClifford Wolf2014-02-15
* Updated ABC and some related changesClifford Wolf2014-02-13
* Disabled "abc -dff" in "make test" for now (waiting for scorr bugfix in ABC)Clifford Wolf2014-02-12
* Added test cases for expose -evert-dffClifford Wolf2014-02-08
* Added splice commandClifford Wolf2014-02-07
* Added counters sat test caseClifford Wolf2014-02-06
* Removed old unused files from tests/Clifford Wolf2014-02-05
* Added test cases for sat commandClifford Wolf2014-02-04
* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-03
* Replaced isim with xsim in tests/tools/autotest.sh, removed xst supportClifford Wolf2014-02-03
* Bugfix in name resolution with generate blocksClifford Wolf2014-01-30