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Author
Age
*
Added "synth" command
Clifford Wolf
2014-09-14
*
Fixed autotest for non-basename arguments
Clifford Wolf
2014-09-06
*
Added tests/various/constmsk_test.ys
Clifford Wolf
2014-09-04
*
Added autotest -e (do not use -noexpr on write_verilog)
Clifford Wolf
2014-08-30
*
Cosmetic changes to FSM tests
Clifford Wolf
2014-08-21
*
Some improvements in FSM mapping and recoding
Clifford Wolf
2014-08-14
*
Added test_verific mode to tests/fsm/generate.py
Clifford Wolf
2014-08-12
*
Added multi-dim memory test (requires iverilog git head)
Clifford Wolf
2014-08-12
*
Fixed FSM mapping for multiple reset-like signals
Clifford Wolf
2014-08-10
*
Some improvements in fsm_opt and fsm_map for FSM with unreachable states
Clifford Wolf
2014-08-09
*
Improved FSM tests
Clifford Wolf
2014-08-08
*
Added FSM test bench
Clifford Wolf
2014-08-08
*
Improved scope resolution of local regs in Verilog+AST frontend
Clifford Wolf
2014-08-05
*
Fixed AST handling of variables declared inside a functions main block
Clifford Wolf
2014-08-05
*
Added "wreduce" to some of the standard test benches
Clifford Wolf
2014-08-03
*
Consolidated hana test benches into fewer files
Clifford Wolf
2014-08-01
*
Added "test_autotb -n <num_iter>" option
Clifford Wolf
2014-08-01
*
Added "make -j{N}" support to "make test"
Clifford Wolf
2014-07-30
*
Renamed "write_autotest" to "test_autotb" and moved to passes/tests/
Clifford Wolf
2014-07-29
*
Added support for "upto" wires to Verilog front- and back-end
Clifford Wolf
2014-07-28
*
Improvements in tests/vloghtb
Clifford Wolf
2014-07-28
*
Added techmap -extern
Clifford Wolf
2014-07-27
*
Added tests/various/.gitignore
Clifford Wolf
2014-07-26
*
Added tests/various/submod_extract.ys
Clifford Wolf
2014-07-26
*
Use "wget -N" in tests/vloghtb/run-test.sh
Clifford Wolf
2014-07-26
*
Renamed some of the test cases in tests/simple to avoid name collisions
Clifford Wolf
2014-07-25
*
Use "opt -fine" in test/vloght/test_mapopt.sh
Clifford Wolf
2014-07-21
*
Added "opt_const -fine" and "opt_reduce -fine"
Clifford Wolf
2014-07-21
*
Various improvements in test/vloghtb
Clifford Wolf
2014-07-21
*
Wider range of cell types supported in "share" pass
Clifford Wolf
2014-07-21
*
Added yet another resource sharing test case
Clifford Wolf
2014-07-20
*
Supercell creation for $div/$mod worked all along, fixed test benches
Clifford Wolf
2014-07-20
*
Improved tests/share/generate.py
Clifford Wolf
2014-07-20
*
Small fix in tests/vloghtb/run-test.sh
Clifford Wolf
2014-07-20
*
Added "miter -equiv -flatten"
Clifford Wolf
2014-07-20
*
Added tests/vloghtb/test_share.sh
Clifford Wolf
2014-07-20
*
Added tests/share for testing "share" supercell creation
Clifford Wolf
2014-07-20
*
Added tests/vloghtb
Clifford Wolf
2014-07-20
*
Added SAT-based write-port sharing to memory_share
Clifford Wolf
2014-07-19
*
Fixed bug in memory_share feedback-to-en code
Clifford Wolf
2014-07-19
*
Added translation from read-feedback to en-signals in memory_share
Clifford Wolf
2014-07-18
*
Bugfix in tests/memories/run-test.sh
Clifford Wolf
2014-07-18
*
added tests/memories
Clifford Wolf
2014-07-18
*
Also simulate unmapped memories in "make test"
Clifford Wolf
2014-07-17
*
Implemented dynamic bit-/part-select for memory writes
Clifford Wolf
2014-07-17
*
Added support for bit/part select to mem2reg rewriter
Clifford Wolf
2014-07-17
*
Added support for constant bit- or part-select for memory writes
Clifford Wolf
2014-07-17
*
Changed tests/techmap/mem_simple_4x1_map for new $mem/$memwr WR_EN interface
Clifford Wolf
2014-07-16
*
Added note to "make test": use git checkout of iverilog
Clifford Wolf
2014-07-16
*
now ignore init attributes on non-register wires in sat command
Clifford Wolf
2014-07-05
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