yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Added yet another resource sharing test case	Clifford Wolf	2014-07-20
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*	Supercell creation for $div/$mod worked all along, fixed test benches	Clifford Wolf	2014-07-20
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*	Improved tests/share/generate.py	Clifford Wolf	2014-07-20
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*	Small fix in tests/vloghtb/run-test.sh	Clifford Wolf	2014-07-20
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*	Added "miter -equiv -flatten"	Clifford Wolf	2014-07-20
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*	Added tests/vloghtb/test_share.sh	Clifford Wolf	2014-07-20
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*	Added tests/share for testing "share" supercell creation	Clifford Wolf	2014-07-20
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*	Added tests/vloghtb	Clifford Wolf	2014-07-20
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*	Added SAT-based write-port sharing to memory_share	Clifford Wolf	2014-07-19
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*	Fixed bug in memory_share feedback-to-en code	Clifford Wolf	2014-07-19
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*	Added translation from read-feedback to en-signals in memory_share	Clifford Wolf	2014-07-18
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*	Bugfix in tests/memories/run-test.sh	Clifford Wolf	2014-07-18
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*	added tests/memories	Clifford Wolf	2014-07-18
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*	Also simulate unmapped memories in "make test"	Clifford Wolf	2014-07-17
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*	Implemented dynamic bit-/part-select for memory writes	Clifford Wolf	2014-07-17
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*	Added support for bit/part select to mem2reg rewriter	Clifford Wolf	2014-07-17
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*	Added support for constant bit- or part-select for memory writes	Clifford Wolf	2014-07-17
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*	Changed tests/techmap/mem_simple_4x1_map for new $mem/$memwr WR_EN interface	Clifford Wolf	2014-07-16
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*	Added note to "make test": use git checkout of iverilog	Clifford Wolf	2014-07-16
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*	now ignore init attributes on non-register wires in sat command	Clifford Wolf	2014-07-05
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*	fixed parsing of constant with comment between size and value	Clifford Wolf	2014-07-02
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*	Fixed handling of mixed real/int ternary expressions	Clifford Wolf	2014-06-25
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*	Little steps in realmath test bench	Clifford Wolf	2014-06-21
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*	Added test case for AstNode::MEM2REG_FL_CMPLX_LHS	Clifford Wolf	2014-06-17
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*	Improved handling of relational op of real values	Clifford Wolf	2014-06-17
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*	Little steps in realmath test bench	Clifford Wolf	2014-06-16
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*	Removed long running tests from tests/simple/realexpr.v (replaced by ↵	Clifford Wolf	2014-06-15
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*	Added tests/realmath to "make test"	Clifford Wolf	2014-06-15
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*	Improved realmath test bench	Clifford Wolf	2014-06-15
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*	improved realmath test bench	Clifford Wolf	2014-06-14
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*	progress in realmath test bench	Clifford Wolf	2014-06-14
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*	added first draft of real math testcase generator	Clifford Wolf	2014-06-14
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*	Added support for math functions	Clifford Wolf	2014-06-14
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*	Added realexpr.v test case	Clifford Wolf	2014-06-14
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*	Added read_verilog -sv options, added support for bit, logic,	Clifford Wolf	2014-06-12
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*	added tests for new verilog features	Clifford Wolf	2014-06-07
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*	Added tests/simple/repwhile.v	Clifford Wolf	2014-06-06
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*	Progress in Verific bindings	Clifford Wolf	2014-03-17
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*	Progress in Verific bindings	Clifford Wolf	2014-03-14
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*	Fixed yosys path in tests/techmap/mem_simple_4x1_runtest.sh	Clifford Wolf	2014-03-11
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*	Use "verilog -noattr" in tests/techmap/mem_simple_4x1 test (for old iverilog)	Clifford Wolf	2014-03-11
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*	Use private namespace in mem_simple_4x1_map	Clifford Wolf	2014-02-21
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*	Added tests/techmap/mem_simple_4x1	Clifford Wolf	2014-02-21
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*	Added vcd2txt.pl and txt2tikztiming.py (tests/tools/...)	Clifford Wolf	2014-02-19
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*	Added frontend (-f) option to autotest.sh	Clifford Wolf	2014-02-15
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*	Updated ABC and some related changes	Clifford Wolf	2014-02-13
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*	Disabled "abc -dff" in "make test" for now (waiting for scorr bugfix in ABC)	Clifford Wolf	2014-02-12
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*	Added test cases for expose -evert-dff	Clifford Wolf	2014-02-08
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*	Added splice command	Clifford Wolf	2014-02-07
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*	Added counters sat test case	Clifford Wolf	2014-02-06
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