| Commit message (Expand) | Author | Age | |
|---|---|---|---|
| * | Fixed a bug in AST frontend for cases with non-blocking assigned variables as... | Clifford Wolf | 2013-04-13 |
| * | Now only use value from "initial" when no matching "always" block is found | Clifford Wolf | 2013-03-31 |
| * | Added test cases from 2012 paper on comparison of foss verilog synthesis tools | Clifford Wolf | 2013-03-31 |
| * | Added k68 (m68k compatible cpu) test case from verilator | Clifford Wolf | 2013-03-31 |
| * | Renamed hansimem.v test case to mem_arst.v | Clifford Wolf | 2013-03-24 |
| * | Added hansimem testcase (memory with async reset) | Clifford Wolf | 2013-03-24 |
| * | Set execute bit on tests/openmsp430/run-synth.sh for real | Clifford Wolf | 2013-03-17 |
| * | set executable flags to run-synth.sh, added .gitignore | Johann Glaser | 2013-03-17 |
| * | added ckeck for Icarus Verilog, otherwise the tests are silently stopped | Johann Glaser | 2013-03-17 |
| * | added more .gitignore files (make test) | Clifford Wolf | 2013-01-05 |
| * | initial import | Clifford Wolf | 2013-01-05 |
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