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* Added tests/realmath to "make test"Clifford Wolf2014-06-15
* Improved realmath test benchClifford Wolf2014-06-15
* improved realmath test benchClifford Wolf2014-06-14
* progress in realmath test benchClifford Wolf2014-06-14
* added first draft of real math testcase generatorClifford Wolf2014-06-14
* Added support for math functionsClifford Wolf2014-06-14
* Added realexpr.v test caseClifford Wolf2014-06-14
* Added read_verilog -sv options, added support for bit, logic,Clifford Wolf2014-06-12
* added tests for new verilog featuresClifford Wolf2014-06-07
* Added tests/simple/repwhile.vClifford Wolf2014-06-06
* Progress in Verific bindingsClifford Wolf2014-03-17
* Progress in Verific bindingsClifford Wolf2014-03-14
* Fixed yosys path in tests/techmap/mem_simple_4x1_runtest.shClifford Wolf2014-03-11
* Use "verilog -noattr" in tests/techmap/mem_simple_4x1 test (for old iverilog)Clifford Wolf2014-03-11
* Use private namespace in mem_simple_4x1_mapClifford Wolf2014-02-21
* Added tests/techmap/mem_simple_4x1Clifford Wolf2014-02-21
* Added vcd2txt.pl and txt2tikztiming.py (tests/tools/...)Clifford Wolf2014-02-19
* Added frontend (-f) option to autotest.shClifford Wolf2014-02-15
* Updated ABC and some related changesClifford Wolf2014-02-13
* Disabled "abc -dff" in "make test" for now (waiting for scorr bugfix in ABC)Clifford Wolf2014-02-12
* Added test cases for expose -evert-dffClifford Wolf2014-02-08
* Added splice commandClifford Wolf2014-02-07
* Added counters sat test caseClifford Wolf2014-02-06
* Removed old unused files from tests/Clifford Wolf2014-02-05
* Added test cases for sat commandClifford Wolf2014-02-04
* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-03
* Replaced isim with xsim in tests/tools/autotest.sh, removed xst supportClifford Wolf2014-02-03
* Bugfix in name resolution with generate blocksClifford Wolf2014-01-30
* Added correct handling of $memwr priorityClifford Wolf2014-01-03
* Added autotest.sh -p optionClifford Wolf2014-01-02
* Use "abc -dff" in "make test"Clifford Wolf2013-12-31
* Fixed commented out techmap call in tests/tools/autotest.shClifford Wolf2013-12-31
* Added proper === and !== support in constant expressionsClifford Wolf2013-12-27
* Added multiplier test case from eda playgroundClifford Wolf2013-12-18
* Added elsif preproc supportClifford Wolf2013-12-18
* Added support for macro argumentsClifford Wolf2013-12-18
* Various improvements in support for generate statementsClifford Wolf2013-12-04
* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-04
* Fix in sincos testbench genClifford Wolf2013-12-04
* Added sincos test caseClifford Wolf2013-12-04
* Renamed stdcells_sim.v to simcells.v and fixed blackbox.vClifford Wolf2013-11-24
* Removed now obsolete test casesClifford Wolf2013-11-24
* Implemented correct handling of signed module parametersClifford Wolf2013-11-24
* Added modelsim support to autotestClifford Wolf2013-11-24
* Another name resolution bugfix for generate blocksClifford Wolf2013-11-20
* Implemented indexed part selectsClifford Wolf2013-11-20
* Implemented part/bit select on memory readClifford Wolf2013-11-20
* Added additional mem2reg testcaseClifford Wolf2013-11-18
* Fixed parsing of default cases when not last caseClifford Wolf2013-11-18
* Fixed handling of power operatorClifford Wolf2013-11-07