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* Improvements in tests/vloghtbClifford Wolf2014-07-28
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* Added techmap -externClifford Wolf2014-07-27
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* Added tests/various/.gitignoreClifford Wolf2014-07-26
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* Added tests/various/submod_extract.ysClifford Wolf2014-07-26
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* Use "wget -N" in tests/vloghtb/run-test.shClifford Wolf2014-07-26
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* Renamed some of the test cases in tests/simple to avoid name collisionsClifford Wolf2014-07-25
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* Use "opt -fine" in test/vloght/test_mapopt.shClifford Wolf2014-07-21
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* Added "opt_const -fine" and "opt_reduce -fine"Clifford Wolf2014-07-21
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* Various improvements in test/vloghtbClifford Wolf2014-07-21
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* Wider range of cell types supported in "share" passClifford Wolf2014-07-21
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* Added yet another resource sharing test caseClifford Wolf2014-07-20
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* Supercell creation for $div/$mod worked all along, fixed test benchesClifford Wolf2014-07-20
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* Improved tests/share/generate.pyClifford Wolf2014-07-20
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* Small fix in tests/vloghtb/run-test.shClifford Wolf2014-07-20
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* Added "miter -equiv -flatten"Clifford Wolf2014-07-20
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* Added tests/vloghtb/test_share.shClifford Wolf2014-07-20
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* Added tests/share for testing "share" supercell creationClifford Wolf2014-07-20
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* Added tests/vloghtbClifford Wolf2014-07-20
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* Added SAT-based write-port sharing to memory_shareClifford Wolf2014-07-19
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* Fixed bug in memory_share feedback-to-en codeClifford Wolf2014-07-19
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* Added translation from read-feedback to en-signals in memory_shareClifford Wolf2014-07-18
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* Bugfix in tests/memories/run-test.shClifford Wolf2014-07-18
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* added tests/memoriesClifford Wolf2014-07-18
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* Also simulate unmapped memories in "make test"Clifford Wolf2014-07-17
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* Implemented dynamic bit-/part-select for memory writesClifford Wolf2014-07-17
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* Added support for bit/part select to mem2reg rewriterClifford Wolf2014-07-17
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* Added support for constant bit- or part-select for memory writesClifford Wolf2014-07-17
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* Changed tests/techmap/mem_simple_4x1_map for new $mem/$memwr WR_EN interfaceClifford Wolf2014-07-16
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* Added note to "make test": use git checkout of iverilogClifford Wolf2014-07-16
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* now ignore init attributes on non-register wires in sat commandClifford Wolf2014-07-05
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* fixed parsing of constant with comment between size and valueClifford Wolf2014-07-02
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* Fixed handling of mixed real/int ternary expressionsClifford Wolf2014-06-25
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* Little steps in realmath test benchClifford Wolf2014-06-21
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* Added test case for AstNode::MEM2REG_FL_CMPLX_LHSClifford Wolf2014-06-17
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* Improved handling of relational op of real valuesClifford Wolf2014-06-17
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* Little steps in realmath test benchClifford Wolf2014-06-16
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* Removed long running tests from tests/simple/realexpr.v (replaced by ↵Clifford Wolf2014-06-15
| | | | tests/realmath)
* Added tests/realmath to "make test"Clifford Wolf2014-06-15
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* Improved realmath test benchClifford Wolf2014-06-15
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* improved realmath test benchClifford Wolf2014-06-14
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* progress in realmath test benchClifford Wolf2014-06-14
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* added first draft of real math testcase generatorClifford Wolf2014-06-14
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* Added support for math functionsClifford Wolf2014-06-14
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* Added realexpr.v test caseClifford Wolf2014-06-14
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* Added read_verilog -sv options, added support for bit, logic,Clifford Wolf2014-06-12
| | | | allways_ff, always_comb, and always_latch
* added tests for new verilog featuresClifford Wolf2014-06-07
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* Added tests/simple/repwhile.vClifford Wolf2014-06-06
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* Progress in Verific bindingsClifford Wolf2014-03-17
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* Progress in Verific bindingsClifford Wolf2014-03-14
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* Fixed yosys path in tests/techmap/mem_simple_4x1_runtest.shClifford Wolf2014-03-11
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