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* Added memory_bram "shuffle_enable" featureClifford Wolf2015-01-04
* Added "memory -bram"Clifford Wolf2015-01-03
* Added memory_bram 'or_next_if_better' featureClifford Wolf2015-01-03
* memory_bram transp supportClifford Wolf2015-01-03
* Progress in memory_bramClifford Wolf2015-01-03
* Added proper clkpol support to memory_bramClifford Wolf2015-01-02
* Fixes and improvements in bram testClifford Wolf2015-01-02
* Progress in bram testbenchClifford Wolf2015-01-02
* Progress in memory_bramClifford Wolf2015-01-02
* Progress in memory_bramClifford Wolf2015-01-02
* Progress in bram testbenchClifford Wolf2015-01-01
* Bram testbench (incomplete)Clifford Wolf2015-01-01
* Added "yosys -qq" to also quiet warning messagesClifford Wolf2014-11-09
* Added support for task and function args in parenthesesClifford Wolf2014-10-27
* Added "synth" commandClifford Wolf2014-09-14
* Fixed autotest for non-basename argumentsClifford Wolf2014-09-06
* Added tests/various/constmsk_test.ysClifford Wolf2014-09-04
* Added autotest -e (do not use -noexpr on write_verilog)Clifford Wolf2014-08-30
* Cosmetic changes to FSM testsClifford Wolf2014-08-21
* Some improvements in FSM mapping and recodingClifford Wolf2014-08-14
* Added test_verific mode to tests/fsm/generate.pyClifford Wolf2014-08-12
* Added multi-dim memory test (requires iverilog git head)Clifford Wolf2014-08-12
* Fixed FSM mapping for multiple reset-like signalsClifford Wolf2014-08-10
* Some improvements in fsm_opt and fsm_map for FSM with unreachable statesClifford Wolf2014-08-09
* Improved FSM testsClifford Wolf2014-08-08
* Added FSM test benchClifford Wolf2014-08-08
* Improved scope resolution of local regs in Verilog+AST frontendClifford Wolf2014-08-05
* Fixed AST handling of variables declared inside a functions main blockClifford Wolf2014-08-05
* Added "wreduce" to some of the standard test benchesClifford Wolf2014-08-03
* Consolidated hana test benches into fewer filesClifford Wolf2014-08-01
* Added "test_autotb -n <num_iter>" optionClifford Wolf2014-08-01
* Added "make -j{N}" support to "make test"Clifford Wolf2014-07-30
* Renamed "write_autotest" to "test_autotb" and moved to passes/tests/Clifford Wolf2014-07-29
* Added support for "upto" wires to Verilog front- and back-endClifford Wolf2014-07-28
* Improvements in tests/vloghtbClifford Wolf2014-07-28
* Added techmap -externClifford Wolf2014-07-27
* Added tests/various/.gitignoreClifford Wolf2014-07-26
* Added tests/various/submod_extract.ysClifford Wolf2014-07-26
* Use "wget -N" in tests/vloghtb/run-test.shClifford Wolf2014-07-26
* Renamed some of the test cases in tests/simple to avoid name collisionsClifford Wolf2014-07-25
* Use "opt -fine" in test/vloght/test_mapopt.shClifford Wolf2014-07-21
* Added "opt_const -fine" and "opt_reduce -fine"Clifford Wolf2014-07-21
* Various improvements in test/vloghtbClifford Wolf2014-07-21
* Wider range of cell types supported in "share" passClifford Wolf2014-07-21
* Added yet another resource sharing test caseClifford Wolf2014-07-20
* Supercell creation for $div/$mod worked all along, fixed test benchesClifford Wolf2014-07-20
* Improved tests/share/generate.pyClifford Wolf2014-07-20
* Small fix in tests/vloghtb/run-test.shClifford Wolf2014-07-20
* Added "miter -equiv -flatten"Clifford Wolf2014-07-20
* Added tests/vloghtb/test_share.shClifford Wolf2014-07-20