yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Added SAT-based write-port sharing to memory_share	Clifford Wolf	2014-07-19
\|
*	Fixed bug in memory_share feedback-to-en code	Clifford Wolf	2014-07-19
\|
*	Added translation from read-feedback to en-signals in memory_share	Clifford Wolf	2014-07-18
\|
*	Bugfix in tests/memories/run-test.sh	Clifford Wolf	2014-07-18
\|
*	added tests/memories	Clifford Wolf	2014-07-18
\|
*	Also simulate unmapped memories in "make test"	Clifford Wolf	2014-07-17
\|
*	Implemented dynamic bit-/part-select for memory writes	Clifford Wolf	2014-07-17
\|
*	Added support for bit/part select to mem2reg rewriter	Clifford Wolf	2014-07-17
\|
*	Added support for constant bit- or part-select for memory writes	Clifford Wolf	2014-07-17
\|
*	Changed tests/techmap/mem_simple_4x1_map for new $mem/$memwr WR_EN interface	Clifford Wolf	2014-07-16
\|
*	Added note to "make test": use git checkout of iverilog	Clifford Wolf	2014-07-16
\|
*	now ignore init attributes on non-register wires in sat command	Clifford Wolf	2014-07-05
\|
*	fixed parsing of constant with comment between size and value	Clifford Wolf	2014-07-02
\|
*	Fixed handling of mixed real/int ternary expressions	Clifford Wolf	2014-06-25
\|
*	Little steps in realmath test bench	Clifford Wolf	2014-06-21
\|
*	Added test case for AstNode::MEM2REG_FL_CMPLX_LHS	Clifford Wolf	2014-06-17
\|
*	Improved handling of relational op of real values	Clifford Wolf	2014-06-17
\|
*	Little steps in realmath test bench	Clifford Wolf	2014-06-16
\|
*	Removed long running tests from tests/simple/realexpr.v (replaced by ↵	Clifford Wolf	2014-06-15
\| \| \| \|	tests/realmath)
*	Added tests/realmath to "make test"	Clifford Wolf	2014-06-15
\|
*	Improved realmath test bench	Clifford Wolf	2014-06-15
\|
*	improved realmath test bench	Clifford Wolf	2014-06-14
\|
*	progress in realmath test bench	Clifford Wolf	2014-06-14
\|
*	added first draft of real math testcase generator	Clifford Wolf	2014-06-14
\|
*	Added support for math functions	Clifford Wolf	2014-06-14
\|
*	Added realexpr.v test case	Clifford Wolf	2014-06-14
\|
*	Added read_verilog -sv options, added support for bit, logic,	Clifford Wolf	2014-06-12
\| \| \| \|	allways_ff, always_comb, and always_latch
*	added tests for new verilog features	Clifford Wolf	2014-06-07
\|
*	Added tests/simple/repwhile.v	Clifford Wolf	2014-06-06
\|
*	Progress in Verific bindings	Clifford Wolf	2014-03-17
\|
*	Progress in Verific bindings	Clifford Wolf	2014-03-14
\|
*	Fixed yosys path in tests/techmap/mem_simple_4x1_runtest.sh	Clifford Wolf	2014-03-11
\|
*	Use "verilog -noattr" in tests/techmap/mem_simple_4x1 test (for old iverilog)	Clifford Wolf	2014-03-11
\|
*	Use private namespace in mem_simple_4x1_map	Clifford Wolf	2014-02-21
\|
*	Added tests/techmap/mem_simple_4x1	Clifford Wolf	2014-02-21
\|
*	Added vcd2txt.pl and txt2tikztiming.py (tests/tools/...)	Clifford Wolf	2014-02-19
\|
*	Added frontend (-f) option to autotest.sh	Clifford Wolf	2014-02-15
\|
*	Updated ABC and some related changes	Clifford Wolf	2014-02-13
\|
*	Disabled "abc -dff" in "make test" for now (waiting for scorr bugfix in ABC)	Clifford Wolf	2014-02-12
\|
*	Added test cases for expose -evert-dff	Clifford Wolf	2014-02-08
\|
*	Added splice command	Clifford Wolf	2014-02-07
\|
*	Added counters sat test case	Clifford Wolf	2014-02-06
\|
*	Removed old unused files from tests/	Clifford Wolf	2014-02-05
\|
*	Added test cases for sat command	Clifford Wolf	2014-02-04
\|
*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03
\|
*	Replaced isim with xsim in tests/tools/autotest.sh, removed xst support	Clifford Wolf	2014-02-03
\|
*	Bugfix in name resolution with generate blocks	Clifford Wolf	2014-01-30
\|
*	Added correct handling of $memwr priority	Clifford Wolf	2014-01-03
\|
*	Added autotest.sh -p option	Clifford Wolf	2014-01-02
\|
*	Use "abc -dff" in "make test"	Clifford Wolf	2013-12-31
\|