yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Use private namespace in mem_simple_4x1_map	Clifford Wolf	2014-02-21
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*	Added tests/techmap/mem_simple_4x1	Clifford Wolf	2014-02-21
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*	Added vcd2txt.pl and txt2tikztiming.py (tests/tools/...)	Clifford Wolf	2014-02-19
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*	Added frontend (-f) option to autotest.sh	Clifford Wolf	2014-02-15
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*	Updated ABC and some related changes	Clifford Wolf	2014-02-13
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*	Disabled "abc -dff" in "make test" for now (waiting for scorr bugfix in ABC)	Clifford Wolf	2014-02-12
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*	Added test cases for expose -evert-dff	Clifford Wolf	2014-02-08
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*	Added splice command	Clifford Wolf	2014-02-07
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*	Added counters sat test case	Clifford Wolf	2014-02-06
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*	Removed old unused files from tests/	Clifford Wolf	2014-02-05
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*	Added test cases for sat command	Clifford Wolf	2014-02-04
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*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03
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*	Replaced isim with xsim in tests/tools/autotest.sh, removed xst support	Clifford Wolf	2014-02-03
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*	Bugfix in name resolution with generate blocks	Clifford Wolf	2014-01-30
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*	Added correct handling of $memwr priority	Clifford Wolf	2014-01-03
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*	Added autotest.sh -p option	Clifford Wolf	2014-01-02
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*	Use "abc -dff" in "make test"	Clifford Wolf	2013-12-31
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*	Fixed commented out techmap call in tests/tools/autotest.sh	Clifford Wolf	2013-12-31
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*	Added proper === and !== support in constant expressions	Clifford Wolf	2013-12-27
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*	Added multiplier test case from eda playground	Clifford Wolf	2013-12-18
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*	Added elsif preproc support	Clifford Wolf	2013-12-18
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*	Added support for macro arguments	Clifford Wolf	2013-12-18
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*	Various improvements in support for generate statements	Clifford Wolf	2013-12-04
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*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04
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*	Fix in sincos testbench gen	Clifford Wolf	2013-12-04
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*	Added sincos test case	Clifford Wolf	2013-12-04
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*	Renamed stdcells_sim.v to simcells.v and fixed blackbox.v	Clifford Wolf	2013-11-24
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*	Removed now obsolete test cases	Clifford Wolf	2013-11-24
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*	Implemented correct handling of signed module parameters	Clifford Wolf	2013-11-24
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*	Added modelsim support to autotest	Clifford Wolf	2013-11-24
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*	Another name resolution bugfix for generate blocks	Clifford Wolf	2013-11-20
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*	Implemented indexed part selects	Clifford Wolf	2013-11-20
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*	Implemented part/bit select on memory read	Clifford Wolf	2013-11-20
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*	Added additional mem2reg testcase	Clifford Wolf	2013-11-18
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*	Fixed parsing of default cases when not last case	Clifford Wolf	2013-11-18
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*	Fixed handling of power operator	Clifford Wolf	2013-11-07
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*	Behavior should be identical now to rev. 0b4a64ac6adbd6 (next: testing ↵	Clifford Wolf	2013-11-02
\| \| \| \|	before constfold fixes)
*	Various ast changes for early expression width detection (prep for constfold ↵	Clifford Wolf	2013-11-02
\| \| \| \|	fixes)
*	Added support for complex set-reset flip-flops in proc_dff	Clifford Wolf	2013-10-24
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*	Improved handling of dff with async resets	Clifford Wolf	2013-10-21
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*	Moved common techlib files to techlibs/common	Clifford Wolf	2013-09-15
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*	Added support for "2**n" shifter encoding	Clifford Wolf	2013-08-12
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*	Added $div and $mod technology mapping	Clifford Wolf	2013-08-09
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*	More fixes in ternary op sign handling	Clifford Wolf	2013-07-12
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*	Fixed sign handling in ternary operator	Clifford Wolf	2013-07-12
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*	Another vloghammer related bugfix	Clifford Wolf	2013-07-11
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*	More fixes in ast expression sign/width handling	Clifford Wolf	2013-07-09
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*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2013-07-09
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\| *	Major redesign of expr width/sign detecion (verilog/ast frontend)	Clifford Wolf	2013-07-09
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* \|	Fixed shift ops with large right hand side	Clifford Wolf	2013-07-09
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