path: root/tests
Commit message (Expand)AuthorAge
* Improved (added -d option)Clifford Wolf2013-05-14
* Some improvements in vcdcd.plClifford Wolf2013-05-14
* Fixed a bug in AST frontend for cases with non-blocking assigned variables as...Clifford Wolf2013-04-13
* Now only use value from "initial" when no matching "always" block is foundClifford Wolf2013-03-31
* Added test cases from 2012 paper on comparison of foss verilog synthesis toolsClifford Wolf2013-03-31
* Added k68 (m68k compatible cpu) test case from verilatorClifford Wolf2013-03-31
* Renamed hansimem.v test case to mem_arst.vClifford Wolf2013-03-24
* Added hansimem testcase (memory with async reset)Clifford Wolf2013-03-24
* Set execute bit on tests/openmsp430/ for realClifford Wolf2013-03-17
* set executable flags to, added .gitignoreJohann Glaser2013-03-17
* added ckeck for Icarus Verilog, otherwise the tests are silently stoppedJohann Glaser2013-03-17
* added more .gitignore files (make test)Clifford Wolf2013-01-05
* initial importClifford Wolf2013-01-05