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* Added tests/various/constmsk_test.ysClifford Wolf2014-09-04
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* Added autotest -e (do not use -noexpr on write_verilog)Clifford Wolf2014-08-30
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* Cosmetic changes to FSM testsClifford Wolf2014-08-21
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* Some improvements in FSM mapping and recodingClifford Wolf2014-08-14
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* Added test_verific mode to tests/fsm/generate.pyClifford Wolf2014-08-12
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* Added multi-dim memory test (requires iverilog git head)Clifford Wolf2014-08-12
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* Fixed FSM mapping for multiple reset-like signalsClifford Wolf2014-08-10
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* Some improvements in fsm_opt and fsm_map for FSM with unreachable statesClifford Wolf2014-08-09
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* Improved FSM testsClifford Wolf2014-08-08
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* Added FSM test benchClifford Wolf2014-08-08
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* Improved scope resolution of local regs in Verilog+AST frontendClifford Wolf2014-08-05
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* Fixed AST handling of variables declared inside a functions main blockClifford Wolf2014-08-05
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* Added "wreduce" to some of the standard test benchesClifford Wolf2014-08-03
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* Consolidated hana test benches into fewer filesClifford Wolf2014-08-01
| | | | | | | | for pf in test_simulation_{always,and,buffer,decoder,inc,mux,nand,nor,or,seq,shifter,sop,techmap,xnor,xor}; do gawk 'FNR == 1 { printf("\n// %s\n",FILENAME); } { gsub("^module *", sprintf("module f%d_",ARGIND)); print; }' \ ${pf}_*_test.v > $pf.v; ../tools/autotest.sh $pf.v; mv -v ${pf}_*_test.v Attic/; done; ..etc..
* Added "test_autotb -n <num_iter>" optionClifford Wolf2014-08-01
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* Added "make -j{N}" support to "make test"Clifford Wolf2014-07-30
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* Renamed "write_autotest" to "test_autotb" and moved to passes/tests/Clifford Wolf2014-07-29
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* Added support for "upto" wires to Verilog front- and back-endClifford Wolf2014-07-28
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* Improvements in tests/vloghtbClifford Wolf2014-07-28
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* Added techmap -externClifford Wolf2014-07-27
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* Added tests/various/.gitignoreClifford Wolf2014-07-26
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* Added tests/various/submod_extract.ysClifford Wolf2014-07-26
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* Use "wget -N" in tests/vloghtb/run-test.shClifford Wolf2014-07-26
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* Renamed some of the test cases in tests/simple to avoid name collisionsClifford Wolf2014-07-25
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* Use "opt -fine" in test/vloght/test_mapopt.shClifford Wolf2014-07-21
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* Added "opt_const -fine" and "opt_reduce -fine"Clifford Wolf2014-07-21
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* Various improvements in test/vloghtbClifford Wolf2014-07-21
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* Wider range of cell types supported in "share" passClifford Wolf2014-07-21
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* Added yet another resource sharing test caseClifford Wolf2014-07-20
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* Supercell creation for $div/$mod worked all along, fixed test benchesClifford Wolf2014-07-20
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* Improved tests/share/generate.pyClifford Wolf2014-07-20
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* Small fix in tests/vloghtb/run-test.shClifford Wolf2014-07-20
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* Added "miter -equiv -flatten"Clifford Wolf2014-07-20
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* Added tests/vloghtb/test_share.shClifford Wolf2014-07-20
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* Added tests/share for testing "share" supercell creationClifford Wolf2014-07-20
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* Added tests/vloghtbClifford Wolf2014-07-20
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* Added SAT-based write-port sharing to memory_shareClifford Wolf2014-07-19
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* Fixed bug in memory_share feedback-to-en codeClifford Wolf2014-07-19
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* Added translation from read-feedback to en-signals in memory_shareClifford Wolf2014-07-18
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* Bugfix in tests/memories/run-test.shClifford Wolf2014-07-18
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* added tests/memoriesClifford Wolf2014-07-18
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* Also simulate unmapped memories in "make test"Clifford Wolf2014-07-17
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* Implemented dynamic bit-/part-select for memory writesClifford Wolf2014-07-17
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* Added support for bit/part select to mem2reg rewriterClifford Wolf2014-07-17
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* Added support for constant bit- or part-select for memory writesClifford Wolf2014-07-17
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* Changed tests/techmap/mem_simple_4x1_map for new $mem/$memwr WR_EN interfaceClifford Wolf2014-07-16
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* Added note to "make test": use git checkout of iverilogClifford Wolf2014-07-16
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* now ignore init attributes on non-register wires in sat commandClifford Wolf2014-07-05
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* fixed parsing of constant with comment between size and valueClifford Wolf2014-07-02
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* Fixed handling of mixed real/int ternary expressionsClifford Wolf2014-06-25
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