From a2d053694b6269bab8871a810142943fac6a3a18 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 4 Dec 2013 09:24:52 +0100 Subject: Fix in sincos testbench gen --- tests/simple/sincos.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/simple/sincos.v b/tests/simple/sincos.v index 66156b68..b3124337 100644 --- a/tests/simple/sincos.v +++ b/tests/simple/sincos.v @@ -39,7 +39,7 @@ input start; input clock; input reset; -(* gentb_constant="0" *) +(* gentb_constant = 1'b0 *) wire reset; always @(posedge clock, posedge reset) begin: DESIGN_PROCESSOR -- cgit v1.2.3