From ae09c89f626d48bb2fa274903a220d32170b033e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 16 Aug 2015 09:50:17 +0200 Subject: Fixed opt_clean handling of inout ports --- passes/opt/opt_clean.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index e6de9d3c..49615d9d 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -90,7 +90,7 @@ void rmunused_module_cells(Module *module, bool verbose) for (auto &it : module->cells_) { Cell *cell = it.second; for (auto &it2 : cell->connections()) { - if (!ct_all.cell_input(cell->type, it2.first)) + if (!ct_all.cell_known(cell->type) || ct_all.cell_output(cell->type, it2.first)) for (auto bit : sigmap(it2.second)) if (bit.wire != nullptr) wire2driver[bit].insert(cell); @@ -115,7 +115,7 @@ void rmunused_module_cells(Module *module, bool verbose) pool bits; for (auto cell : queue) for (auto &it : cell->connections()) - if (!ct_all.cell_output(cell->type, it.first)) + if (!ct_all.cell_known(cell->type) || ct_all.cell_input(cell->type, it.first)) for (auto bit : sigmap(it.second)) bits.insert(bit); -- cgit v1.2.3