From ae798d3fd5dc6bdd82083cce3994f449b829995e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 24 Nov 2013 17:55:46 +0100 Subject: Fixed xilinx/example_sim_counter test bench --- techlibs/xilinx/example_sim_counter/run_sim.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/xilinx/example_sim_counter/run_sim.sh b/techlibs/xilinx/example_sim_counter/run_sim.sh index e26d00db..b8354c00 100644 --- a/techlibs/xilinx/example_sim_counter/run_sim.sh +++ b/techlibs/xilinx/example_sim_counter/run_sim.sh @@ -8,7 +8,7 @@ XILINX_DIR=/opt/Xilinx/14.5/ISE_DS/ISE iverilog -o testbench_gold counter_tb.v counter.v iverilog -o testbench_gate counter_tb.v testbench_synth.v \ - $XILINX_DIR/verilog/src/{glbl,unisims/{FDRE,LUT1,LUT2,LUT3,LUT4,LUT5,LUT6}}.v + $XILINX_DIR/verilog/src/{glbl,unisims/{FDRE,LUT1,LUT2,LUT3,LUT4,LUT5,LUT6,BUFGP,IBUF}}.v ./testbench_gold > testbench_gold.txt ./testbench_gate > testbench_gate.txt -- cgit v1.2.3