From b6acbc82e6a2954d453188a9997da2a30731ddac Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 2 Aug 2014 20:54:30 +0200
Subject: Bugfix in "techmap -extern"

---
 kernel/rtlil.cc           | 26 ++++++++++++++++----------
 passes/techmap/techmap.cc |  1 +
 2 files changed, 17 insertions(+), 10 deletions(-)

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 56c631f3..792474af 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -815,25 +815,34 @@ namespace {
 void RTLIL::Module::check()
 {
 #ifndef NDEBUG
+	std::vector<bool> ports_declared;
 	for (auto &it : wires_) {
 		log_assert(this == it.second->module);
 		log_assert(it.first == it.second->name);
 		log_assert(!it.first.empty());
 		log_assert(it.second->width >= 0);
 		log_assert(it.second->port_id >= 0);
-		for (auto &it2 : it.second->attributes) {
+		for (auto &it2 : it.second->attributes)
 			log_assert(!it2.first.empty());
-		}
+		if (it.second->port_id) {
+			log_assert(it.second->port_input || it.second->port_output);
+			if (SIZE(ports_declared) < it.second->port_id)
+				ports_declared.resize(it.second->port_id);
+			log_assert(ports_declared[it.second->port_id-1] == false);
+			ports_declared[it.second->port_id-1] = true;
+		} else
+			log_assert(!it.second->port_input && !it.second->port_output);
 	}
+	for (auto port_declared : ports_declared)
+		log_assert(port_declared == true);
 
 	for (auto &it : memories) {
 		log_assert(it.first == it.second->name);
 		log_assert(!it.first.empty());
 		log_assert(it.second->width >= 0);
 		log_assert(it.second->size >= 0);
-		for (auto &it2 : it.second->attributes) {
+		for (auto &it2 : it.second->attributes)
 			log_assert(!it2.first.empty());
-		}
 	}
 
 	for (auto &it : cells_) {
@@ -845,12 +854,10 @@ void RTLIL::Module::check()
 			log_assert(!it2.first.empty());
 			it2.second.check();
 		}
-		for (auto &it2 : it.second->attributes) {
+		for (auto &it2 : it.second->attributes)
 			log_assert(!it2.first.empty());
-		}
-		for (auto &it2 : it.second->parameters) {
+		for (auto &it2 : it.second->parameters)
 			log_assert(!it2.first.empty());
-		}
 		InternalCellChecker checker(this, it.second);
 		checker.check();
 	}
@@ -867,9 +874,8 @@ void RTLIL::Module::check()
 		it.second.check();
 	}
 
-	for (auto &it : attributes) {
+	for (auto &it : attributes)
 		log_assert(!it.first.empty());
-	}
 #endif
 }
 
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index c639cc48..74a51550 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -504,6 +504,7 @@ struct TechmapWorker
 
 									RTLIL::Wire *new_wire = tpl->addWire(port_name, wire);
 									wire->port_input = false;
+									wire->port_id = 0;
 
 									for (int i = 0; i < wire->width; i++) {
 										port_new2old_map[RTLIL::SigBit(new_wire, i)] = RTLIL::SigBit(wire, i);
-- 
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