From cbe77bf84465ea0c4120e865189b07329b862468 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 29 Jan 2014 12:15:38 +0100 Subject: presentation progress --- manual/.gitignore | 1 + manual/PRESENTATION_Intro.tex | 60 +++++++++++++++++++++++++++++++++-- manual/PRESENTATION_Intro/.gitignore | 4 +++ manual/PRESENTATION_Intro/Makefile | 10 ++++++ manual/PRESENTATION_Intro/counter.v | 12 +++++++ manual/PRESENTATION_Intro/counter.ys | 26 +++++++++++++++ manual/PRESENTATION_Intro/mycells.lib | 38 ++++++++++++++++++++++ manual/PRESENTATION_Intro/mycells.v | 23 ++++++++++++++ manual/presentation.sh | 1 + manual/presentation.tex | 1 + 10 files changed, 174 insertions(+), 2 deletions(-) create mode 100644 manual/PRESENTATION_Intro/.gitignore create mode 100644 manual/PRESENTATION_Intro/Makefile create mode 100644 manual/PRESENTATION_Intro/counter.v create mode 100644 manual/PRESENTATION_Intro/counter.ys create mode 100644 manual/PRESENTATION_Intro/mycells.lib create mode 100644 manual/PRESENTATION_Intro/mycells.v diff --git a/manual/.gitignore b/manual/.gitignore index 8ae9cbde..110f65b1 100644 --- a/manual/.gitignore +++ b/manual/.gitignore @@ -8,4 +8,5 @@ *.toc *.snm *.nav +*.vrb *.ok diff --git a/manual/PRESENTATION_Intro.tex b/manual/PRESENTATION_Intro.tex index 9cbe9944..6693ad2f 100644 --- a/manual/PRESENTATION_Intro.tex +++ b/manual/PRESENTATION_Intro.tex @@ -153,7 +153,7 @@ Things Yosys can do: \begin{itemize} \item Read and process (most of) modern Verilog-2005 code. \item Perform all kinds of operations on netlist (RTL, Logic, Gate). -\item Perform logic optimiziations and gate mapping with ABC\footnote{\url{http://www.eecs.berkeley.edu/~alanmi/abc/}}. +\item Perform logic optimiziations and gate mapping with ABC\footnote[frame]{\url{http://www.eecs.berkeley.edu/~alanmi/abc/}}. \end{itemize} \bigskip @@ -165,7 +165,7 @@ Things Yosys can't do: \bigskip A typical flow combines Yosys with with a low-level implementation tool, such -as Qflow\footnote{\url{http://opencircuitdesign.com/qflow/}} for ASIC designs. +as Qflow\footnote[frame]{\url{http://opencircuitdesign.com/qflow/}} for ASIC designs. \end{frame} @@ -318,3 +318,59 @@ as Qflow\footnote{\url{http://opencircuitdesign.com/qflow/}} for ASIC designs. \end{frame} +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\subsection{Running the Synthesis Script} + +\begin{frame}[fragile]{\subsecname{} -- Verilog Source: \tt counter.v} +\lstinputlisting[xleftmargin=1cm, language=Verilog]{PRESENTATION_Intro/counter.v} +\end{frame} + +\begin{frame}[fragile]{\subsecname{} -- Cell Library: \tt mycells.lib} +\begin{columns} +\column[t]{5cm} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=liberty, lastline=20]{PRESENTATION_Intro/mycells.lib} +\column[t]{5cm} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=liberty, firstline=21]{PRESENTATION_Intro/mycells.lib} +\end{columns} +\end{frame} + +\begin{frame}[t, fragile]{\subsecname{} -- Step 1/4} +\begin{verbatim} +read_verilog counter.v +hierarchy -check -top counter +\end{verbatim} + +\vfill +\includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{PRESENTATION_Intro/counter_00.pdf} +\end{frame} + +\begin{frame}[t, fragile]{\subsecname{} -- Step 2/4} +\begin{verbatim} +proc; opt; memory; opt; fsm; opt +\end{verbatim} + +\vfill +\includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{PRESENTATION_Intro/counter_01.pdf} +\end{frame} + +\begin{frame}[t, fragile]{\subsecname{} -- Step 3/4} +\begin{verbatim} +techmap; opt +\end{verbatim} + +\vfill +\includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{PRESENTATION_Intro/counter_02.pdf} +\end{frame} + +\begin{frame}[t, fragile]{\subsecname{} -- Step 4/4} +\begin{verbatim} +dfflibmap -liberty mycells.lib +abc -liberty mycells.lib +clean +\end{verbatim} + +\vfill +\includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{PRESENTATION_Intro/counter_03.pdf} +\end{frame} + diff --git a/manual/PRESENTATION_Intro/.gitignore b/manual/PRESENTATION_Intro/.gitignore new file mode 100644 index 00000000..d0c4618a --- /dev/null +++ b/manual/PRESENTATION_Intro/.gitignore @@ -0,0 +1,4 @@ +counter_00.dot +counter_01.dot +counter_02.dot +counter_03.dot diff --git a/manual/PRESENTATION_Intro/Makefile b/manual/PRESENTATION_Intro/Makefile new file mode 100644 index 00000000..abc354e4 --- /dev/null +++ b/manual/PRESENTATION_Intro/Makefile @@ -0,0 +1,10 @@ + +all: counter_00.pdf counter_01.pdf counter_02.pdf counter_03.pdf + +counter_00.pdf: counter.v counter.ys mycells.lib + ../../yosys counter.ys + +counter_01.pdf: counter_00.pdf +counter_02.pdf: counter_00.pdf +counter_03.pdf: counter_00.pdf + diff --git a/manual/PRESENTATION_Intro/counter.v b/manual/PRESENTATION_Intro/counter.v new file mode 100644 index 00000000..36b878e3 --- /dev/null +++ b/manual/PRESENTATION_Intro/counter.v @@ -0,0 +1,12 @@ +module counter (clk, rst, en, count); + + input clk, rst, en; + output reg [1:0] count; + + always @(posedge clk) + if (rst) + count <= 2'd0; + else if (en) + count <= count + 2'd1; + +endmodule diff --git a/manual/PRESENTATION_Intro/counter.ys b/manual/PRESENTATION_Intro/counter.ys new file mode 100644 index 00000000..68fe0308 --- /dev/null +++ b/manual/PRESENTATION_Intro/counter.ys @@ -0,0 +1,26 @@ +# read design +read_verilog counter.v +hierarchy -check -top counter + +show -format pdf -prefix counter_00 + +# the high-level stuff +proc; opt; memory; opt; fsm; opt + +show -format pdf -prefix counter_01 + +# mapping to internal cell library +techmap; splitnets -ports; opt + +show -format pdf -prefix counter_02 + +# mapping flip-flops to mycells.lib +dfflibmap -liberty mycells.lib + +# mapping logic to mycells.lib +abc -liberty mycells.lib + +# cleanup +clean + +show -lib mycells.v -format pdf -prefix counter_03 diff --git a/manual/PRESENTATION_Intro/mycells.lib b/manual/PRESENTATION_Intro/mycells.lib new file mode 100644 index 00000000..a0204d7e --- /dev/null +++ b/manual/PRESENTATION_Intro/mycells.lib @@ -0,0 +1,38 @@ +library(demo) { + cell(BUF) { + area: 6; + pin(A) { direction: input; } + pin(Y) { direction: output; + function: "A"; } + } + cell(NOT) { + area: 3; + pin(A) { direction: input; } + pin(Y) { direction: output; + function: "A'"; } + } + cell(NAND) { + area: 4; + pin(A) { direction: input; } + pin(B) { direction: input; } + pin(Y) { direction: output; + function: "(A*B)'"; } + } + cell(NOR) { + area: 4; + pin(A) { direction: input; } + pin(B) { direction: input; } + pin(Y) { direction: output; + function: "(A+B)'"; } + } + cell(DFF) { + area: 18; + ff(IQ, IQN) { clocked_on: C; + next_state: D; } + pin(C) { direction: input; + clock: true; } + pin(D) { direction: input; } + pin(Q) { direction: output; + function: "IQ"; } + } +} diff --git a/manual/PRESENTATION_Intro/mycells.v b/manual/PRESENTATION_Intro/mycells.v new file mode 100644 index 00000000..802f5871 --- /dev/null +++ b/manual/PRESENTATION_Intro/mycells.v @@ -0,0 +1,23 @@ + +module NOT(A, Y); +input A; +output Y = ~A; +endmodule + +module NAND(A, B, Y); +input A, B; +output Y = ~(A & B); +endmodule + +module NOR(A, B, Y); +input A, B; +output Y = ~(A | B); +endmodule + +module DFF(C, D, Q); +input C, D; +output reg Q; +always @(posedge C) + Q <= D; +endmodule + diff --git a/manual/presentation.sh b/manual/presentation.sh index 3a55b939..530d0b8c 100755 --- a/manual/presentation.sh +++ b/manual/presentation.sh @@ -26,6 +26,7 @@ PDFTEX_OPT="-shell-escape -halt-on-error" if ! $fast_mode; then md5sum *.aux *.snm *.nav *.toc > autoloop.old + make -C PRESENTATION_Intro fi set -ex diff --git a/manual/presentation.tex b/manual/presentation.tex index 4b445192..ac3c73a7 100644 --- a/manual/presentation.tex +++ b/manual/presentation.tex @@ -23,6 +23,7 @@ \usepackage{multirow} \usepackage{booktabs} \usepackage{listings} +\usepackage{setspace} \usepackage{skull} \usepackage{tikz} -- cgit v1.2.3