From ed62fcdbe224207434c5f643734f2627264826c5 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 9 Jul 2013 23:53:55 +0200 Subject: Fixed sign propagation in bit-wise operators --- frontends/ast/genrtlil.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 83077822..7a9c8ba6 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -896,6 +896,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) int width = std::max(left.width, right.width); if (width_hint > 0) width = width_hint; + is_signed = children[0]->is_signed && children[1]->is_signed; return binop2rtlil(this, type_name, width, left, right); } -- cgit v1.2.3