From f5c0ed6c79010df60cdb7ab3ea4c26ed3d61e2f1 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 17 Oct 2013 02:41:59 +0200 Subject: Fixed detection of major wires in opt_clean --- passes/opt/opt_clean.cc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 2ea60c03..f8811bac 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -112,6 +112,9 @@ static bool compare_signals(RTLIL::SigSpec &s1, RTLIL::SigSpec &s2) if (w1->port_input != w2->port_input) return w2->port_input; + if (w1->port_output != w2->port_output) + return w2->port_output; + if (w1->name[0] != w2->name[0]) return w2->name[0] == '\\'; -- cgit v1.2.3