From 1e2440e7ed6979bdee2f80116d6c3a429b604e25 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 1 Feb 2014 13:04:49 +0100
Subject: Added note about SystemVerilog assert statement to README

---
 README | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'README')

diff --git a/README b/README
index 307f594b..f0c9bc74 100644
--- a/README
+++ b/README
@@ -270,6 +270,11 @@ Verilog Attributes and non-standard features
   for everything that comes after the {* ... *} statement. (Reset
   by adding an empty {* *} statement.)
 
+- The "assert" statement from SystemVerilog is supported in its most basic
+  form. In module context: "assert property (<expression>);" and within an
+  always block: "assert(<expression>);". It is transformed to a $assert cell
+  that is supported by the "sat" and "write_btor" commands.
+
 
 Workarounds for known build problems
 ====================================
-- 
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