From ac2be2d892e3311b89744306e8c29445f588f590 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 20 Nov 2013 11:05:58 +0100
Subject: Fixed name resolution of local tasks and functions in generate block

---
 README | 1 -
 1 file changed, 1 deletion(-)

(limited to 'README')

diff --git a/README b/README
index 76b8a122..aa68da25 100644
--- a/README
+++ b/README
@@ -292,7 +292,6 @@ Roadmap / Large-scale TODOs
    - yosys-bigsim: https://github.com/cliffordwolf/yosys-bigsim
 
 - Missing Verilog-2005 features to be implemented soon:
-  - Fix corner cases with contextual name lookup
   - Indexed part selects
 
 - Technology mapping for real-world applications
-- 
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