From c89ceee219b5a6412a64f585caeceb5db9528fe4 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 18 Sep 2015 10:01:08 +0200
Subject: Added $finish and $display to README

---
 README | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'README')

diff --git a/README b/README
index 0a1c2068..868fd90e 100644
--- a/README
+++ b/README
@@ -367,6 +367,10 @@ Verilog Attributes and non-standard features
   expressions as <size>. If the expression is not a simple identifier, it
   must be put in parentheses. Examples: WIDTH'd42, (4+2)'b101010
 
+- The system tasks $finish and $display are supported in initial blocks
+  in and unconditional context (only if/case statements on parameters
+  and constant values). The intended use for this is synthesis-time DRC.
+
 
 Supported features from SystemVerilog
 =====================================
-- 
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