From 6aa792c864444324a1b140c2b63bd860f0cc3914 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 24 Jul 2014 22:47:57 +0200 Subject: Replaced more old SigChunk programming patterns --- backends/autotest/autotest.cc | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'backends/autotest') diff --git a/backends/autotest/autotest.cc b/backends/autotest/autotest.cc index 028d1f37..db49880a 100644 --- a/backends/autotest/autotest.cc +++ b/backends/autotest/autotest.cc @@ -119,10 +119,9 @@ static void autotest(FILE *f, RTLIL::Design *design) if ((*it4)->type == RTLIL::ST0 || (*it4)->type == RTLIL::ST1) continue; RTLIL::SigSpec &signal = (*it4)->signal; - for (size_t i = 0; i < signal.chunks().size(); i++) { - if (signal.chunks()[i].wire == wire) + for (auto &c : signal.chunks()) + if (c.wire == wire) is_clksignal = true; - } } if (is_clksignal && wire->attributes.count("\\gentb_constant") == 0) { signal_clk[idy("sig", mod->name, wire->name)] = wire->width; -- cgit v1.2.3