From a233762a815fc180b371f699e865a7d7aed77bca Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 22 Jul 2014 19:56:17 +0200
Subject: SigSpec refactoring: renamed chunks and width to __chunks and __width

---
 backends/autotest/autotest.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'backends/autotest')

diff --git a/backends/autotest/autotest.cc b/backends/autotest/autotest.cc
index 3e2fab00..e7fbfe7a 100644
--- a/backends/autotest/autotest.cc
+++ b/backends/autotest/autotest.cc
@@ -119,8 +119,8 @@ static void autotest(FILE *f, RTLIL::Design *design)
 					if ((*it4)->type == RTLIL::ST0 || (*it4)->type == RTLIL::ST1)
 						continue;
 					RTLIL::SigSpec &signal = (*it4)->signal;
-					for (size_t i = 0; i < signal.chunks.size(); i++) {
-						if (signal.chunks[i].wire == wire)
+					for (size_t i = 0; i < signal.__chunks.size(); i++) {
+						if (signal.__chunks[i].wire == wire)
 							is_clksignal = true;
 					}
 				}
-- 
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