From f7bd0a523203ed52713ecde56c1cfb89df4d48af Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 7 Mar 2014 15:56:10 +0100
Subject: Use log_abort() and log_assert() in BTOR backend

---
 backends/btor/btor.cc | 35 +++++++++++++++++------------------
 1 file changed, 17 insertions(+), 18 deletions(-)

(limited to 'backends/btor/btor.cc')

diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index 03ef183a..45f7b414 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -28,7 +28,6 @@
 #include "kernel/celltypes.h"
 #include "kernel/log.h"
 #include <string>
-#include <assert.h>
 #include <math.h>
 
 struct BtorDumperConfig
@@ -244,7 +243,7 @@ struct BtorDumper
 				return it->second;
 			}
 		}
-		assert(false);
+		log_abort();
 		return -1;
 	}
 	
@@ -283,7 +282,7 @@ struct BtorDumper
 		}
 		else
 			log("writing const error\n");		
-		assert(false);
+		log_abort();
 		return -1;
 	}
 	
@@ -302,7 +301,7 @@ struct BtorDumper
 			else 
 			{
 				int wire_line_num = dump_wire(chunk->wire);
-				assert(wire_line_num>0);
+				log_assert(wire_line_num>0);
 				++line_num;
 				str = stringf("%d slice %d %d %d %d;2", line_num, chunk->width, wire_line_num, 
 					chunk->width + chunk->offset - 1, chunk->offset);
@@ -329,12 +328,12 @@ struct BtorDumper
 			{
 				int l1, l2, w1, w2;
 				l1 = dump_sigchunk(&s.chunks[0]);
-				assert(l1>0);
+				log_assert(l1>0);
 				w1 = s.chunks[0].width;
 				for (unsigned i=1; i < s.chunks.size(); ++i)
 				{
 					l2 = dump_sigchunk(&s.chunks[i]);
-					assert(l2>0);
+					log_assert(l2>0);
 					w2 = s.chunks[i].width;
 					++line_num;
 					str = stringf("%d concat %d %d %d", line_num, w1+w2, l2, l1);
@@ -374,7 +373,7 @@ struct BtorDumper
 				l = line_num;
 			}
 		}
-		assert(l>0);
+		log_assert(l>0);
 		return l;
 	}
 	
@@ -390,8 +389,8 @@ struct BtorDumper
 				log("writing assert cell - %s\n", cstr(cell->type));
 				const RTLIL::SigSpec* expr = &cell->connections.at(RTLIL::IdString("\\A"));
 				const RTLIL::SigSpec* en = &cell->connections.at(RTLIL::IdString("\\EN"));
-				assert(expr->width == 1);
-				assert(en->width == 1);
+				log_assert(expr->width == 1);
+				log_assert(en->width == 1);
 				int expr_line = dump_sigspec(expr, 1);
 				int en_line = dump_sigspec(en, 1);
 				int one_line = ++line_num;
@@ -444,7 +443,7 @@ struct BtorDumper
 				log("writing unary cell - %s\n", cstr(cell->type));
 				int w = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
 				int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
-				assert(output_width == 1);
+				log_assert(output_width == 1);
 				int l = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\A")), w);
 				if(cell->type == "$logic_not" && w > 1)
 				{
@@ -470,7 +469,7 @@ struct BtorDumper
 			{
 				log("writing binary cell - %s\n", cstr(cell->type));
 				int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
-				assert(!(cell->type == "$eq" || cell->type == "$ne" || cell->type == "$eqx" || cell->type == "$nex" ||
+				log_assert(!(cell->type == "$eq" || cell->type == "$ne" || cell->type == "$eqx" || cell->type == "$nex" ||
 					cell->type == "$ge" || cell->type == "$gt") || output_width == 1);
 				bool l1_signed = cell->parameters.at(RTLIL::IdString("\\A_SIGNED")).as_bool();
 				bool l2_signed = cell->parameters.at(RTLIL::IdString("\\B_SIGNED")).as_bool();
@@ -511,7 +510,7 @@ struct BtorDumper
 				int l1_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
 				int l2_width = 	cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
 				
-				assert(l1_signed == l2_signed);
+				log_assert(l1_signed == l2_signed);
 				l1_width = l1_width > output_width ? l1_width : output_width;					
 				l1_width = l1_width > l2_width ? l1_width : l2_width;
 				l2_width = l2_width > l1_width ? l2_width : l1_width;
@@ -592,7 +591,7 @@ struct BtorDumper
 			{
 				log("writing binary cell - %s\n", cstr(cell->type));
 				int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
-				assert(output_width == 1);
+				log_assert(output_width == 1);
 				int l1 = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\A")), output_width);
 				int l2 = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\B")), output_width);
 				int l1_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
@@ -653,7 +652,7 @@ struct BtorDumper
 				for(unsigned i=0; i<cell_output->chunks.size(); ++i)
 				{
 					output_width = cell_output->chunks[i].width;
-					assert( output_width == cell_output->chunks[i].wire->width);//full reg is given the next value
+					log_assert( output_width == cell_output->chunks[i].wire->width);//full reg is given the next value
 					int reg = dump_wire(cell_output->chunks[i].wire);//register
 					int slice = value;
 					if(cell_output->chunks.size()>1)
@@ -760,11 +759,11 @@ struct BtorDumper
 				log("writing slice cell\n");
 				const RTLIL::SigSpec* input = &cell->connections.at(RTLIL::IdString("\\A"));
 				int input_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
-				assert(input->width == input_width);
+				log_assert(input->width == input_width);
 				int input_line = dump_sigspec(input, input_width);
 				const RTLIL::SigSpec* output = &cell->connections.at(RTLIL::IdString("\\Y"));
 				int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
-				assert(output->width == output_width);
+				log_assert(output->width == output_width);
 				int offset = cell->parameters.at(RTLIL::IdString("\\OFFSET")).as_int();	
 				++line_num;
 				str = stringf("%d %s %d %d %d %d", line_num, cell_type_translation.at(cell->type).c_str(), output_width, input_line, output_width+offset-1, offset);	
@@ -776,11 +775,11 @@ struct BtorDumper
 				log("writing concat cell\n");
 				const RTLIL::SigSpec* input_a = &cell->connections.at(RTLIL::IdString("\\A"));
 				int input_a_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
-				assert(input_a->width == input_a_width);
+				log_assert(input_a->width == input_a_width);
 				int input_a_line = dump_sigspec(input_a, input_a_width);
 				const RTLIL::SigSpec* input_b = &cell->connections.at(RTLIL::IdString("\\B"));
 				int input_b_width = cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
-				assert(input_b->width == input_b_width);
+				log_assert(input_b->width == input_b_width);
 				int input_b_line = dump_sigspec(input_b, input_b_width);
 				++line_num;
 				str = stringf("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type).c_str(), input_a_width+input_b_width, 
-- 
cgit v1.2.3


From a233762a815fc180b371f699e865a7d7aed77bca Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 22 Jul 2014 19:56:17 +0200
Subject: SigSpec refactoring: renamed chunks and width to __chunks and __width

---
 backends/btor/btor.cc | 80 +++++++++++++++++++++++++--------------------------
 1 file changed, 40 insertions(+), 40 deletions(-)

(limited to 'backends/btor/btor.cc')

diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index 45f7b414..428e9a88 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -196,7 +196,7 @@ struct BtorDumper
 					RTLIL::SigSpec* cell_output = get_cell_output(cell);
 					int cell_line = dump_cell(cell);				
 
-					if(dep_set.size()==1 && wire->width == cell_output->width)
+					if(dep_set.size()==1 && wire->width == cell_output->__width)
 					{
 						wire_line = cell_line;
 						break;
@@ -205,17 +205,17 @@ struct BtorDumper
 					{
 						int prev_wire_line=0; //previously dumped wire line
 						int start_bit=0;
-						for(unsigned j=0; j<cell_output->chunks.size(); ++j)
+						for(unsigned j=0; j<cell_output->__chunks.size(); ++j)
 						{
-							start_bit+=cell_output->chunks[j].width;
-							if(cell_output->chunks[j].wire->name == wire->name)
+							start_bit+=cell_output->__chunks[j].width;
+							if(cell_output->__chunks[j].wire->name == wire->name)
 							{
 								prev_wire_line = wire_line;
 								wire_line = ++line_num;
-								str = stringf("%d slice %d %d %d %d;1", line_num, cell_output->chunks[j].width,
- 									cell_line, start_bit-1, start_bit-cell_output->chunks[j].width);
+								str = stringf("%d slice %d %d %d %d;1", line_num, cell_output->__chunks[j].width,
+ 									cell_line, start_bit-1, start_bit-cell_output->__chunks[j].width);
 								fprintf(f, "%s\n", str.c_str());
-								wire_width += cell_output->chunks[j].width;
+								wire_width += cell_output->__chunks[j].width;
 								if(prev_wire_line!=0)
 								{
 									++line_num;
@@ -231,7 +231,7 @@ struct BtorDumper
 				{
 					log(" - checking sigmap\n");						
 					RTLIL::SigSpec s = RTLIL::SigSpec(wire);
-					wire_line = dump_sigspec(&s, s.width);
+					wire_line = dump_sigspec(&s, s.__width);
 					line_ref[wire->name]=wire_line;
 				}
 				line_ref[wire->name]=wire_line;
@@ -320,21 +320,21 @@ struct BtorDumper
 		auto it = sig_ref.find(s);
 		if(it == std::end(sig_ref))
 		{
-			if (s.chunks.size() == 1) 
+			if (s.__chunks.size() == 1) 
 			{
-				l = dump_sigchunk(&s.chunks[0]);
+				l = dump_sigchunk(&s.__chunks[0]);
 			} 
 			else 
 			{
 				int l1, l2, w1, w2;
-				l1 = dump_sigchunk(&s.chunks[0]);
+				l1 = dump_sigchunk(&s.__chunks[0]);
 				log_assert(l1>0);
-				w1 = s.chunks[0].width;
-				for (unsigned i=1; i < s.chunks.size(); ++i)
+				w1 = s.__chunks[0].width;
+				for (unsigned i=1; i < s.__chunks.size(); ++i)
 				{
-					l2 = dump_sigchunk(&s.chunks[i]);
+					l2 = dump_sigchunk(&s.__chunks[i]);
 					log_assert(l2>0);
-					w2 = s.chunks[i].width;
+					w2 = s.__chunks[i].width;
 					++line_num;
 					str = stringf("%d concat %d %d %d", line_num, w1+w2, l2, l1);
 					fprintf(f, "%s\n", str.c_str());
@@ -350,22 +350,22 @@ struct BtorDumper
 			l = it->second;
 		}
 		
-		if (expected_width != s.width)
+		if (expected_width != s.__width)
 		{
 			log(" - changing width of sigspec\n");
 			//TODO: this block may not be needed anymore, due to explicit type conversion by "splice" command
-			if(expected_width > s.width)
+			if(expected_width > s.__width)
 			{
 				//TODO: case the signal is signed
 				++line_num;
-				str = stringf ("%d zero %d", line_num, expected_width - s.width);
+				str = stringf ("%d zero %d", line_num, expected_width - s.__width);
 				fprintf(f, "%s\n", str.c_str());
 				++line_num;
 				str = stringf ("%d concat %d %d %d", line_num, expected_width, line_num-1, l);
 				fprintf(f, "%s\n", str.c_str());
 				l = line_num;
 			}
-			else if(expected_width < s.width)
+			else if(expected_width < s.__width)
 			{
 				++line_num;
 				str = stringf ("%d slice %d %d %d %d;3", line_num, expected_width, l, expected_width-1, 0);
@@ -389,8 +389,8 @@ struct BtorDumper
 				log("writing assert cell - %s\n", cstr(cell->type));
 				const RTLIL::SigSpec* expr = &cell->connections.at(RTLIL::IdString("\\A"));
 				const RTLIL::SigSpec* en = &cell->connections.at(RTLIL::IdString("\\EN"));
-				log_assert(expr->width == 1);
-				log_assert(en->width == 1);
+				log_assert(expr->__width == 1);
+				log_assert(en->__width == 1);
 				int expr_line = dump_sigspec(expr, 1);
 				int en_line = dump_sigspec(en, 1);
 				int one_line = ++line_num;
@@ -649,13 +649,13 @@ struct BtorDumper
 				const RTLIL::SigSpec* cell_output = &cell->connections.at(RTLIL::IdString("\\Q"));
 				int value = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\D")), output_width);
 				unsigned start_bit = 0;
-				for(unsigned i=0; i<cell_output->chunks.size(); ++i)
+				for(unsigned i=0; i<cell_output->__chunks.size(); ++i)
 				{
-					output_width = cell_output->chunks[i].width;
-					log_assert( output_width == cell_output->chunks[i].wire->width);//full reg is given the next value
-					int reg = dump_wire(cell_output->chunks[i].wire);//register
+					output_width = cell_output->__chunks[i].width;
+					log_assert( output_width == cell_output->__chunks[i].wire->width);//full reg is given the next value
+					int reg = dump_wire(cell_output->__chunks[i].wire);//register
 					int slice = value;
-					if(cell_output->chunks.size()>1)
+					if(cell_output->__chunks.size()>1)
 					{
 						start_bit+=output_width;
 						slice = ++line_num;
@@ -759,11 +759,11 @@ struct BtorDumper
 				log("writing slice cell\n");
 				const RTLIL::SigSpec* input = &cell->connections.at(RTLIL::IdString("\\A"));
 				int input_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
-				log_assert(input->width == input_width);
+				log_assert(input->__width == input_width);
 				int input_line = dump_sigspec(input, input_width);
 				const RTLIL::SigSpec* output = &cell->connections.at(RTLIL::IdString("\\Y"));
 				int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
-				log_assert(output->width == output_width);
+				log_assert(output->__width == output_width);
 				int offset = cell->parameters.at(RTLIL::IdString("\\OFFSET")).as_int();	
 				++line_num;
 				str = stringf("%d %s %d %d %d %d", line_num, cell_type_translation.at(cell->type).c_str(), output_width, input_line, output_width+offset-1, offset);	
@@ -775,11 +775,11 @@ struct BtorDumper
 				log("writing concat cell\n");
 				const RTLIL::SigSpec* input_a = &cell->connections.at(RTLIL::IdString("\\A"));
 				int input_a_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
-				log_assert(input_a->width == input_a_width);
+				log_assert(input_a->__width == input_a_width);
 				int input_a_line = dump_sigspec(input_a, input_a_width);
 				const RTLIL::SigSpec* input_b = &cell->connections.at(RTLIL::IdString("\\B"));
 				int input_b_width = cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
-				log_assert(input_b->width == input_b_width);
+				log_assert(input_b->__width == input_b_width);
 				int input_b_line = dump_sigspec(input_b, input_b_width);
 				++line_num;
 				str = stringf("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type).c_str(), input_a_width+input_b_width, 
@@ -843,11 +843,11 @@ struct BtorDumper
 			log(" - %s\n", cstr(it->second->type));
 			if (cell->type == "$memrd")
 			{
-				for(unsigned i=0; i<output_sig->chunks.size(); ++i)
+				for(unsigned i=0; i<output_sig->__chunks.size(); ++i)
 				{
-					RTLIL::Wire *w = output_sig->chunks[i].wire;
+					RTLIL::Wire *w = output_sig->__chunks[i].wire;
 					RTLIL::IdString wire_id = w->name;
-					inter_wire_map[wire_id].insert(WireInfo(cell->name,&output_sig->chunks[i]));
+					inter_wire_map[wire_id].insert(WireInfo(cell->name,&output_sig->__chunks[i]));
 				}
 			}
 			else if(cell->type == "$memwr")
@@ -856,22 +856,22 @@ struct BtorDumper
 			}
 			else if(cell->type == "$dff" || cell->type == "$adff" || cell->type == "$dffsr")
 			{
-				RTLIL::IdString wire_id = output_sig->chunks[0].wire->name;
-				for(unsigned i=0; i<output_sig->chunks.size(); ++i)
+				RTLIL::IdString wire_id = output_sig->__chunks[0].wire->name;
+				for(unsigned i=0; i<output_sig->__chunks.size(); ++i)
 				{
-					RTLIL::Wire *w = output_sig->chunks[i].wire;
+					RTLIL::Wire *w = output_sig->__chunks[i].wire;
 					RTLIL::IdString wire_id = w->name;
-					inter_wire_map[wire_id].insert(WireInfo(cell->name,&output_sig->chunks[i]));
+					inter_wire_map[wire_id].insert(WireInfo(cell->name,&output_sig->__chunks[i]));
 					basic_wires[wire_id] = true;
 				}
 			}
 			else 
 			{
-				for(unsigned i=0; i<output_sig->chunks.size(); ++i)
+				for(unsigned i=0; i<output_sig->__chunks.size(); ++i)
 				{
-					RTLIL::Wire *w = output_sig->chunks[i].wire;
+					RTLIL::Wire *w = output_sig->__chunks[i].wire;
 					RTLIL::IdString wire_id = w->name;
-					inter_wire_map[wire_id].insert(WireInfo(cell->name,&output_sig->chunks[i]));
+					inter_wire_map[wire_id].insert(WireInfo(cell->name,&output_sig->__chunks[i]));
 				}
 			}
 		}
-- 
cgit v1.2.3


From 4b4048bc5feba1ab05c7a63f12c0a17879cb7e04 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 22 Jul 2014 20:15:14 +0200
Subject: SigSpec refactoring: using the accessor functions everywhere

---
 backends/btor/btor.cc | 80 +++++++++++++++++++++++++--------------------------
 1 file changed, 40 insertions(+), 40 deletions(-)

(limited to 'backends/btor/btor.cc')

diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index 428e9a88..7853160e 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -196,7 +196,7 @@ struct BtorDumper
 					RTLIL::SigSpec* cell_output = get_cell_output(cell);
 					int cell_line = dump_cell(cell);				
 
-					if(dep_set.size()==1 && wire->width == cell_output->__width)
+					if(dep_set.size()==1 && wire->width == cell_output->size())
 					{
 						wire_line = cell_line;
 						break;
@@ -205,17 +205,17 @@ struct BtorDumper
 					{
 						int prev_wire_line=0; //previously dumped wire line
 						int start_bit=0;
-						for(unsigned j=0; j<cell_output->__chunks.size(); ++j)
+						for(unsigned j=0; j<cell_output->chunks().size(); ++j)
 						{
-							start_bit+=cell_output->__chunks[j].width;
-							if(cell_output->__chunks[j].wire->name == wire->name)
+							start_bit+=cell_output->chunks()[j].width;
+							if(cell_output->chunks()[j].wire->name == wire->name)
 							{
 								prev_wire_line = wire_line;
 								wire_line = ++line_num;
-								str = stringf("%d slice %d %d %d %d;1", line_num, cell_output->__chunks[j].width,
- 									cell_line, start_bit-1, start_bit-cell_output->__chunks[j].width);
+								str = stringf("%d slice %d %d %d %d;1", line_num, cell_output->chunks()[j].width,
+ 									cell_line, start_bit-1, start_bit-cell_output->chunks()[j].width);
 								fprintf(f, "%s\n", str.c_str());
-								wire_width += cell_output->__chunks[j].width;
+								wire_width += cell_output->chunks()[j].width;
 								if(prev_wire_line!=0)
 								{
 									++line_num;
@@ -231,7 +231,7 @@ struct BtorDumper
 				{
 					log(" - checking sigmap\n");						
 					RTLIL::SigSpec s = RTLIL::SigSpec(wire);
-					wire_line = dump_sigspec(&s, s.__width);
+					wire_line = dump_sigspec(&s, s.size());
 					line_ref[wire->name]=wire_line;
 				}
 				line_ref[wire->name]=wire_line;
@@ -320,21 +320,21 @@ struct BtorDumper
 		auto it = sig_ref.find(s);
 		if(it == std::end(sig_ref))
 		{
-			if (s.__chunks.size() == 1) 
+			if (s.chunks().size() == 1) 
 			{
-				l = dump_sigchunk(&s.__chunks[0]);
+				l = dump_sigchunk(&s.chunks()[0]);
 			} 
 			else 
 			{
 				int l1, l2, w1, w2;
-				l1 = dump_sigchunk(&s.__chunks[0]);
+				l1 = dump_sigchunk(&s.chunks()[0]);
 				log_assert(l1>0);
-				w1 = s.__chunks[0].width;
-				for (unsigned i=1; i < s.__chunks.size(); ++i)
+				w1 = s.chunks()[0].width;
+				for (unsigned i=1; i < s.chunks().size(); ++i)
 				{
-					l2 = dump_sigchunk(&s.__chunks[i]);
+					l2 = dump_sigchunk(&s.chunks()[i]);
 					log_assert(l2>0);
-					w2 = s.__chunks[i].width;
+					w2 = s.chunks()[i].width;
 					++line_num;
 					str = stringf("%d concat %d %d %d", line_num, w1+w2, l2, l1);
 					fprintf(f, "%s\n", str.c_str());
@@ -350,22 +350,22 @@ struct BtorDumper
 			l = it->second;
 		}
 		
-		if (expected_width != s.__width)
+		if (expected_width != s.size())
 		{
 			log(" - changing width of sigspec\n");
 			//TODO: this block may not be needed anymore, due to explicit type conversion by "splice" command
-			if(expected_width > s.__width)
+			if(expected_width > s.size())
 			{
 				//TODO: case the signal is signed
 				++line_num;
-				str = stringf ("%d zero %d", line_num, expected_width - s.__width);
+				str = stringf ("%d zero %d", line_num, expected_width - s.size());
 				fprintf(f, "%s\n", str.c_str());
 				++line_num;
 				str = stringf ("%d concat %d %d %d", line_num, expected_width, line_num-1, l);
 				fprintf(f, "%s\n", str.c_str());
 				l = line_num;
 			}
-			else if(expected_width < s.__width)
+			else if(expected_width < s.size())
 			{
 				++line_num;
 				str = stringf ("%d slice %d %d %d %d;3", line_num, expected_width, l, expected_width-1, 0);
@@ -389,8 +389,8 @@ struct BtorDumper
 				log("writing assert cell - %s\n", cstr(cell->type));
 				const RTLIL::SigSpec* expr = &cell->connections.at(RTLIL::IdString("\\A"));
 				const RTLIL::SigSpec* en = &cell->connections.at(RTLIL::IdString("\\EN"));
-				log_assert(expr->__width == 1);
-				log_assert(en->__width == 1);
+				log_assert(expr->size() == 1);
+				log_assert(en->size() == 1);
 				int expr_line = dump_sigspec(expr, 1);
 				int en_line = dump_sigspec(en, 1);
 				int one_line = ++line_num;
@@ -649,13 +649,13 @@ struct BtorDumper
 				const RTLIL::SigSpec* cell_output = &cell->connections.at(RTLIL::IdString("\\Q"));
 				int value = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\D")), output_width);
 				unsigned start_bit = 0;
-				for(unsigned i=0; i<cell_output->__chunks.size(); ++i)
+				for(unsigned i=0; i<cell_output->chunks().size(); ++i)
 				{
-					output_width = cell_output->__chunks[i].width;
-					log_assert( output_width == cell_output->__chunks[i].wire->width);//full reg is given the next value
-					int reg = dump_wire(cell_output->__chunks[i].wire);//register
+					output_width = cell_output->chunks()[i].width;
+					log_assert( output_width == cell_output->chunks()[i].wire->width);//full reg is given the next value
+					int reg = dump_wire(cell_output->chunks()[i].wire);//register
 					int slice = value;
-					if(cell_output->__chunks.size()>1)
+					if(cell_output->chunks().size()>1)
 					{
 						start_bit+=output_width;
 						slice = ++line_num;
@@ -759,11 +759,11 @@ struct BtorDumper
 				log("writing slice cell\n");
 				const RTLIL::SigSpec* input = &cell->connections.at(RTLIL::IdString("\\A"));
 				int input_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
-				log_assert(input->__width == input_width);
+				log_assert(input->size() == input_width);
 				int input_line = dump_sigspec(input, input_width);
 				const RTLIL::SigSpec* output = &cell->connections.at(RTLIL::IdString("\\Y"));
 				int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
-				log_assert(output->__width == output_width);
+				log_assert(output->size() == output_width);
 				int offset = cell->parameters.at(RTLIL::IdString("\\OFFSET")).as_int();	
 				++line_num;
 				str = stringf("%d %s %d %d %d %d", line_num, cell_type_translation.at(cell->type).c_str(), output_width, input_line, output_width+offset-1, offset);	
@@ -775,11 +775,11 @@ struct BtorDumper
 				log("writing concat cell\n");
 				const RTLIL::SigSpec* input_a = &cell->connections.at(RTLIL::IdString("\\A"));
 				int input_a_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
-				log_assert(input_a->__width == input_a_width);
+				log_assert(input_a->size() == input_a_width);
 				int input_a_line = dump_sigspec(input_a, input_a_width);
 				const RTLIL::SigSpec* input_b = &cell->connections.at(RTLIL::IdString("\\B"));
 				int input_b_width = cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
-				log_assert(input_b->__width == input_b_width);
+				log_assert(input_b->size() == input_b_width);
 				int input_b_line = dump_sigspec(input_b, input_b_width);
 				++line_num;
 				str = stringf("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type).c_str(), input_a_width+input_b_width, 
@@ -843,11 +843,11 @@ struct BtorDumper
 			log(" - %s\n", cstr(it->second->type));
 			if (cell->type == "$memrd")
 			{
-				for(unsigned i=0; i<output_sig->__chunks.size(); ++i)
+				for(unsigned i=0; i<output_sig->chunks().size(); ++i)
 				{
-					RTLIL::Wire *w = output_sig->__chunks[i].wire;
+					RTLIL::Wire *w = output_sig->chunks()[i].wire;
 					RTLIL::IdString wire_id = w->name;
-					inter_wire_map[wire_id].insert(WireInfo(cell->name,&output_sig->__chunks[i]));
+					inter_wire_map[wire_id].insert(WireInfo(cell->name,&output_sig->chunks()[i]));
 				}
 			}
 			else if(cell->type == "$memwr")
@@ -856,22 +856,22 @@ struct BtorDumper
 			}
 			else if(cell->type == "$dff" || cell->type == "$adff" || cell->type == "$dffsr")
 			{
-				RTLIL::IdString wire_id = output_sig->__chunks[0].wire->name;
-				for(unsigned i=0; i<output_sig->__chunks.size(); ++i)
+				RTLIL::IdString wire_id = output_sig->chunks()[0].wire->name;
+				for(unsigned i=0; i<output_sig->chunks().size(); ++i)
 				{
-					RTLIL::Wire *w = output_sig->__chunks[i].wire;
+					RTLIL::Wire *w = output_sig->chunks()[i].wire;
 					RTLIL::IdString wire_id = w->name;
-					inter_wire_map[wire_id].insert(WireInfo(cell->name,&output_sig->__chunks[i]));
+					inter_wire_map[wire_id].insert(WireInfo(cell->name,&output_sig->chunks()[i]));
 					basic_wires[wire_id] = true;
 				}
 			}
 			else 
 			{
-				for(unsigned i=0; i<output_sig->__chunks.size(); ++i)
+				for(unsigned i=0; i<output_sig->chunks().size(); ++i)
 				{
-					RTLIL::Wire *w = output_sig->__chunks[i].wire;
+					RTLIL::Wire *w = output_sig->chunks()[i].wire;
 					RTLIL::IdString wire_id = w->name;
-					inter_wire_map[wire_id].insert(WireInfo(cell->name,&output_sig->__chunks[i]));
+					inter_wire_map[wire_id].insert(WireInfo(cell->name,&output_sig->chunks()[i]));
 				}
 			}
 		}
-- 
cgit v1.2.3


From 28b3fd05fa9cf6d469fdec95e247a7ffe5bc001d Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 22 Jul 2014 20:58:44 +0200
Subject: SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only,
 created interim RTLIL::SigSpec::chunks_rw()

---
 backends/btor/btor.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'backends/btor/btor.cc')

diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index 7853160e..9139749c 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -45,9 +45,9 @@ struct BtorDumperConfig
 struct WireInfo
 {
 	RTLIL::IdString cell_name;
-	RTLIL::SigChunk *chunk;
+	const RTLIL::SigChunk *chunk;
 
-	WireInfo(RTLIL::IdString c, RTLIL::SigChunk* ch) : cell_name(c), chunk(ch) { }
+	WireInfo(RTLIL::IdString c, const RTLIL::SigChunk* ch) : cell_name(c), chunk(ch) { }
 };
 
 struct WireInfoOrder
-- 
cgit v1.2.3


From 5826670009e1018734de49aaf1554cb8a43d09d7 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 25 Jul 2014 14:23:31 +0200
Subject: Various RTLIL::SigSpec related code cleanups

---
 backends/btor/btor.cc | 42 +++++++++++++++++++++---------------------
 1 file changed, 21 insertions(+), 21 deletions(-)

(limited to 'backends/btor/btor.cc')

diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index 9139749c..096c6029 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -207,15 +207,15 @@ struct BtorDumper
 						int start_bit=0;
 						for(unsigned j=0; j<cell_output->chunks().size(); ++j)
 						{
-							start_bit+=cell_output->chunks()[j].width;
-							if(cell_output->chunks()[j].wire->name == wire->name)
+							start_bit+=cell_output->chunks().at(j).width;
+							if(cell_output->chunks().at(j).wire->name == wire->name)
 							{
 								prev_wire_line = wire_line;
 								wire_line = ++line_num;
-								str = stringf("%d slice %d %d %d %d;1", line_num, cell_output->chunks()[j].width,
- 									cell_line, start_bit-1, start_bit-cell_output->chunks()[j].width);
+								str = stringf("%d slice %d %d %d %d;1", line_num, cell_output->chunks().at(j).width,
+									cell_line, start_bit-1, start_bit-cell_output->chunks().at(j).width);
 								fprintf(f, "%s\n", str.c_str());
-								wire_width += cell_output->chunks()[j].width;
+								wire_width += cell_output->chunks().at(j).width;
 								if(prev_wire_line!=0)
 								{
 									++line_num;
@@ -320,21 +320,21 @@ struct BtorDumper
 		auto it = sig_ref.find(s);
 		if(it == std::end(sig_ref))
 		{
-			if (s.chunks().size() == 1) 
+			if (s.is_chunk())
 			{
-				l = dump_sigchunk(&s.chunks()[0]);
+				l = dump_sigchunk(&s.chunks().front());
 			} 
 			else 
 			{
 				int l1, l2, w1, w2;
-				l1 = dump_sigchunk(&s.chunks()[0]);
+				l1 = dump_sigchunk(&s.chunks().front());
 				log_assert(l1>0);
-				w1 = s.chunks()[0].width;
+				w1 = s.chunks().front().width;
 				for (unsigned i=1; i < s.chunks().size(); ++i)
 				{
-					l2 = dump_sigchunk(&s.chunks()[i]);
+					l2 = dump_sigchunk(&s.chunks().at(i));
 					log_assert(l2>0);
-					w2 = s.chunks()[i].width;
+					w2 = s.chunks().at(i).width;
 					++line_num;
 					str = stringf("%d concat %d %d %d", line_num, w1+w2, l2, l1);
 					fprintf(f, "%s\n", str.c_str());
@@ -651,9 +651,9 @@ struct BtorDumper
 				unsigned start_bit = 0;
 				for(unsigned i=0; i<cell_output->chunks().size(); ++i)
 				{
-					output_width = cell_output->chunks()[i].width;
-					log_assert( output_width == cell_output->chunks()[i].wire->width);//full reg is given the next value
-					int reg = dump_wire(cell_output->chunks()[i].wire);//register
+					output_width = cell_output->chunks().at(i).width;
+					log_assert( output_width == cell_output->chunks().at(i).wire->width);//full reg is given the next value
+					int reg = dump_wire(cell_output->chunks().at(i).wire);//register
 					int slice = value;
 					if(cell_output->chunks().size()>1)
 					{
@@ -845,9 +845,9 @@ struct BtorDumper
 			{
 				for(unsigned i=0; i<output_sig->chunks().size(); ++i)
 				{
-					RTLIL::Wire *w = output_sig->chunks()[i].wire;
+					RTLIL::Wire *w = output_sig->chunks().at(i).wire;
 					RTLIL::IdString wire_id = w->name;
-					inter_wire_map[wire_id].insert(WireInfo(cell->name,&output_sig->chunks()[i]));
+					inter_wire_map[wire_id].insert(WireInfo(cell->name,&output_sig->chunks().at(i)));
 				}
 			}
 			else if(cell->type == "$memwr")
@@ -856,12 +856,12 @@ struct BtorDumper
 			}
 			else if(cell->type == "$dff" || cell->type == "$adff" || cell->type == "$dffsr")
 			{
-				RTLIL::IdString wire_id = output_sig->chunks()[0].wire->name;
+				RTLIL::IdString wire_id = output_sig->chunks().front().wire->name;
 				for(unsigned i=0; i<output_sig->chunks().size(); ++i)
 				{
-					RTLIL::Wire *w = output_sig->chunks()[i].wire;
+					RTLIL::Wire *w = output_sig->chunks().at(i).wire;
 					RTLIL::IdString wire_id = w->name;
-					inter_wire_map[wire_id].insert(WireInfo(cell->name,&output_sig->chunks()[i]));
+					inter_wire_map[wire_id].insert(WireInfo(cell->name,&output_sig->chunks().at(i)));
 					basic_wires[wire_id] = true;
 				}
 			}
@@ -869,9 +869,9 @@ struct BtorDumper
 			{
 				for(unsigned i=0; i<output_sig->chunks().size(); ++i)
 				{
-					RTLIL::Wire *w = output_sig->chunks()[i].wire;
+					RTLIL::Wire *w = output_sig->chunks().at(i).wire;
 					RTLIL::IdString wire_id = w->name;
-					inter_wire_map[wire_id].insert(WireInfo(cell->name,&output_sig->chunks()[i]));
+					inter_wire_map[wire_id].insert(WireInfo(cell->name,&output_sig->chunks().at(i)));
 				}
 			}
 		}
-- 
cgit v1.2.3


From cc4f10883bcc5f0a3c1b4f0937e60be3c6a1b121 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 26 Jul 2014 11:58:03 +0200
Subject: Renamed RTLIL::{Module,Cell}::connections to connections_

---
 backends/btor/btor.cc | 68 +++++++++++++++++++++++++--------------------------
 1 file changed, 34 insertions(+), 34 deletions(-)

(limited to 'backends/btor/btor.cc')

diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index 096c6029..46edec9c 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -387,8 +387,8 @@ struct BtorDumper
 			if(cell->type == "$assert")
 			{
 				log("writing assert cell - %s\n", cstr(cell->type));
-				const RTLIL::SigSpec* expr = &cell->connections.at(RTLIL::IdString("\\A"));
-				const RTLIL::SigSpec* en = &cell->connections.at(RTLIL::IdString("\\EN"));
+				const RTLIL::SigSpec* expr = &cell->connections_.at(RTLIL::IdString("\\A"));
+				const RTLIL::SigSpec* en = &cell->connections_.at(RTLIL::IdString("\\EN"));
 				log_assert(expr->size() == 1);
 				log_assert(en->size() == 1);
 				int expr_line = dump_sigspec(expr, 1);
@@ -420,7 +420,7 @@ struct BtorDumper
 				int w = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
 				int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
 				w = w>output_width ? w:output_width; //padding of w
-				int l = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\A")), w);				
+				int l = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\A")), w);				
 				int cell_line = l;
 				if(cell->type != "$pos")
 				{	
@@ -444,7 +444,7 @@ struct BtorDumper
 				int w = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
 				int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
 				log_assert(output_width == 1);
-				int l = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\A")), w);
+				int l = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\A")), w);
 				if(cell->type == "$logic_not" && w > 1)
 				{
 					++line_num;
@@ -481,8 +481,8 @@ struct BtorDumper
 				l1_width = l1_width > l2_width ? l1_width : l2_width;
 				l2_width = l2_width > l1_width ? l2_width : l1_width;
 
-				int l1 = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\A")), l1_width);
-				int l2 = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\B")), l2_width);
+				int l1 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\A")), l1_width);
+				int l2 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\B")), l2_width);
 				
 				++line_num;
 				std::string op = cell_type_translation.at(cell->type);
@@ -515,8 +515,8 @@ struct BtorDumper
 				l1_width = l1_width > l2_width ? l1_width : l2_width;
 				l2_width = l2_width > l1_width ? l2_width : l1_width;
 
-				int l1 = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\A")), l1_width);
-				int l2 = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\B")), l2_width);
+				int l1 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\A")), l1_width);
+				int l2 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\B")), l2_width);
 				
 				++line_num;
 				std::string op = cell_type_translation.at(cell->type);
@@ -550,8 +550,8 @@ struct BtorDumper
 				l1_width = pow(2, ceil(log(l1_width)/log(2)));
 				int l2_width = 	cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
 				//assert(l2_width <= ceil(log(l1_width)/log(2)) );
-				int l1 = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\A")), l1_width);
-				int l2 = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\B")), ceil(log(l1_width)/log(2)));
+				int l1 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\A")), l1_width);
+				int l2 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\B")), ceil(log(l1_width)/log(2)));
 				int cell_output = ++line_num;
 				str = stringf ("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type).c_str(), l1_width, l1, l2);
 				fprintf(f, "%s\n", str.c_str());
@@ -559,7 +559,7 @@ struct BtorDumper
 				if(l2_width > ceil(log(l1_width)/log(2)))
 				{
 					int extra_width = l2_width - ceil(log(l1_width)/log(2));
-					l2 = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\B")), l2_width);
+					l2 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\B")), l2_width);
 					++line_num;
 					str = stringf ("%d slice %d %d %d %d;6", line_num, extra_width, l2, l2_width-1, l2_width-extra_width);
 					fprintf(f, "%s\n", str.c_str());
@@ -592,8 +592,8 @@ struct BtorDumper
 				log("writing binary cell - %s\n", cstr(cell->type));
 				int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
 				log_assert(output_width == 1);
-				int l1 = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\A")), output_width);
-				int l2 = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\B")), output_width);
+				int l1 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\A")), output_width);
+				int l2 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\B")), output_width);
 				int l1_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
 				int l2_width = 	cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
 				if(l1_width >1)
@@ -628,9 +628,9 @@ struct BtorDumper
 			{
 				log("writing mux cell\n");
 				int output_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int();
-				int l1 = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\A")), output_width);
-				int l2 = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\B")), output_width);
-				int s = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\S")), 1);
+				int l1 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\A")), output_width);
+				int l2 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\B")), output_width);
+				int s = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\S")), 1);
 				++line_num;
 				str = stringf ("%d %s %d %d %d %d", 
 					line_num, cell_type_translation.at(cell->type).c_str(), output_width, s, l2, l1);//if s is 0 then l1, if s is 1 then l2 //according to the implementation of mux cell
@@ -644,10 +644,10 @@ struct BtorDumper
 				log("writing cell - %s\n", cstr(cell->type));
 				int output_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int();
 				log(" - width is %d\n", output_width);
-				int cond = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\CLK")), 1);
+				int cond = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\CLK")), 1);
 				bool polarity = cell->parameters.at(RTLIL::IdString("\\CLK_POLARITY")).as_bool();
-				const RTLIL::SigSpec* cell_output = &cell->connections.at(RTLIL::IdString("\\Q"));
-				int value = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\D")), output_width);
+				const RTLIL::SigSpec* cell_output = &cell->connections_.at(RTLIL::IdString("\\Q"));
+				int value = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\D")), output_width);
 				unsigned start_bit = 0;
 				for(unsigned i=0; i<cell_output->chunks().size(); ++i)
 				{
@@ -665,9 +665,9 @@ struct BtorDumper
 					}
 					if(cell->type == "$dffsr")
 					{
-						int sync_reset = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\CLR")), 1);
+						int sync_reset = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\CLR")), 1);
 						bool sync_reset_pol = cell->parameters.at(RTLIL::IdString("\\CLR_POLARITY")).as_bool();
-						int sync_reset_value = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\SET")),
+						int sync_reset_value = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\SET")),
 							output_width);
 						bool sync_reset_value_pol = cell->parameters.at(RTLIL::IdString("\\SET_POLARITY")).as_bool();
 						++line_num;
@@ -685,7 +685,7 @@ struct BtorDumper
 					int next = line_num;
 					if(cell->type == "$adff")
 					{
-						int async_reset = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\ARST")), 1);
+						int async_reset = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\ARST")), 1);
 						bool async_reset_pol = cell->parameters.at(RTLIL::IdString("\\ARST_POLARITY")).as_bool();
 						int async_reset_value = dump_const(&cell->parameters.at(RTLIL::IdString("\\ARST_VALUE")),
 							output_width, 0);
@@ -710,7 +710,7 @@ struct BtorDumper
 				str = cell->parameters.at(RTLIL::IdString("\\MEMID")).decode_string();
 				int mem = dump_memory(module->memories.at(RTLIL::IdString(str.c_str())));
 				int address_width = cell->parameters.at(RTLIL::IdString("\\ABITS")).as_int();
-				int address = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\ADDR")), address_width);
+				int address = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\ADDR")), address_width);
 				int data_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int();
 				++line_num;
 				str = stringf("%d read %d %d %d", line_num, data_width, mem, address);	
@@ -722,13 +722,13 @@ struct BtorDumper
 				log("writing memwr cell\n");
 				if (cell->parameters.at("\\CLK_ENABLE").as_bool() == false)
 					log_error("The btor backen does not support $memwr cells without built-in registers. Run memory_dff (but with -wr_only).\n");
-				int clk = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\CLK")), 1);
+				int clk = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\CLK")), 1);
 				bool polarity = cell->parameters.at(RTLIL::IdString("\\CLK_POLARITY")).as_bool();
-				int enable = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\EN")), 1);
+				int enable = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\EN")), 1);
 				int address_width = cell->parameters.at(RTLIL::IdString("\\ABITS")).as_int();
-				int address = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\ADDR")), address_width);
+				int address = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\ADDR")), address_width);
 				int data_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int();
-				int data = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\DATA")), data_width);
+				int data = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\DATA")), data_width);
 				str = cell->parameters.at(RTLIL::IdString("\\MEMID")).decode_string();
 				int mem = dump_memory(module->memories.at(RTLIL::IdString(str.c_str())));
 				++line_num;
@@ -757,11 +757,11 @@ struct BtorDumper
 			else if(cell->type == "$slice")
 			{
 				log("writing slice cell\n");
-				const RTLIL::SigSpec* input = &cell->connections.at(RTLIL::IdString("\\A"));
+				const RTLIL::SigSpec* input = &cell->connections_.at(RTLIL::IdString("\\A"));
 				int input_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
 				log_assert(input->size() == input_width);
 				int input_line = dump_sigspec(input, input_width);
-				const RTLIL::SigSpec* output = &cell->connections.at(RTLIL::IdString("\\Y"));
+				const RTLIL::SigSpec* output = &cell->connections_.at(RTLIL::IdString("\\Y"));
 				int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
 				log_assert(output->size() == output_width);
 				int offset = cell->parameters.at(RTLIL::IdString("\\OFFSET")).as_int();	
@@ -773,11 +773,11 @@ struct BtorDumper
 			else if(cell->type == "$concat")
 			{
 				log("writing concat cell\n");
-				const RTLIL::SigSpec* input_a = &cell->connections.at(RTLIL::IdString("\\A"));
+				const RTLIL::SigSpec* input_a = &cell->connections_.at(RTLIL::IdString("\\A"));
 				int input_a_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
 				log_assert(input_a->size() == input_a_width);
 				int input_a_line = dump_sigspec(input_a, input_a_width);
-				const RTLIL::SigSpec* input_b = &cell->connections.at(RTLIL::IdString("\\B"));
+				const RTLIL::SigSpec* input_b = &cell->connections_.at(RTLIL::IdString("\\B"));
 				int input_b_width = cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
 				log_assert(input_b->size() == input_b_width);
 				int input_b_line = dump_sigspec(input_b, input_b_width);
@@ -801,7 +801,7 @@ struct BtorDumper
 		RTLIL::SigSpec *output_sig = nullptr;
 		if (cell->type == "$memrd")
 		{
-			output_sig = &cell->connections.at(RTLIL::IdString("\\DATA"));
+			output_sig = &cell->connections_.at(RTLIL::IdString("\\DATA"));
 		}
 		else if(cell->type == "$memwr" || cell->type == "$assert")
 		{
@@ -809,11 +809,11 @@ struct BtorDumper
 		}
 		else if(cell->type == "$dff" || cell->type == "$adff" || cell->type == "$dffsr")
 		{
-			output_sig = &cell->connections.at(RTLIL::IdString("\\Q"));
+			output_sig = &cell->connections_.at(RTLIL::IdString("\\Q"));
 		}
 		else 
 		{
-			output_sig = &cell->connections.at(RTLIL::IdString("\\Y"));
+			output_sig = &cell->connections_.at(RTLIL::IdString("\\Y"));
 		}
 		return output_sig;
 	}
-- 
cgit v1.2.3


From b7dda723022ad00c6c0089be888eab319953faa8 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 26 Jul 2014 14:32:50 +0200
Subject: Changed users of cell->connections_ to the new API (sed command)

git grep -l 'connections_' | xargs sed -i -r -e '
	s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
	s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
	s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
	s/(->|\.)connections_.push_back/\1connect/g;
	s/(->|\.)connections_/\1connections()/g;'
---
 backends/btor/btor.cc | 68 +++++++++++++++++++++++++--------------------------
 1 file changed, 34 insertions(+), 34 deletions(-)

(limited to 'backends/btor/btor.cc')

diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index 46edec9c..0316f7ab 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -387,8 +387,8 @@ struct BtorDumper
 			if(cell->type == "$assert")
 			{
 				log("writing assert cell - %s\n", cstr(cell->type));
-				const RTLIL::SigSpec* expr = &cell->connections_.at(RTLIL::IdString("\\A"));
-				const RTLIL::SigSpec* en = &cell->connections_.at(RTLIL::IdString("\\EN"));
+				const RTLIL::SigSpec* expr = &cell->connections().at(RTLIL::IdString("\\A"));
+				const RTLIL::SigSpec* en = &cell->connections().at(RTLIL::IdString("\\EN"));
 				log_assert(expr->size() == 1);
 				log_assert(en->size() == 1);
 				int expr_line = dump_sigspec(expr, 1);
@@ -420,7 +420,7 @@ struct BtorDumper
 				int w = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
 				int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
 				w = w>output_width ? w:output_width; //padding of w
-				int l = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\A")), w);				
+				int l = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\A")), w);				
 				int cell_line = l;
 				if(cell->type != "$pos")
 				{	
@@ -444,7 +444,7 @@ struct BtorDumper
 				int w = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
 				int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
 				log_assert(output_width == 1);
-				int l = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\A")), w);
+				int l = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\A")), w);
 				if(cell->type == "$logic_not" && w > 1)
 				{
 					++line_num;
@@ -481,8 +481,8 @@ struct BtorDumper
 				l1_width = l1_width > l2_width ? l1_width : l2_width;
 				l2_width = l2_width > l1_width ? l2_width : l1_width;
 
-				int l1 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\A")), l1_width);
-				int l2 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\B")), l2_width);
+				int l1 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\A")), l1_width);
+				int l2 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\B")), l2_width);
 				
 				++line_num;
 				std::string op = cell_type_translation.at(cell->type);
@@ -515,8 +515,8 @@ struct BtorDumper
 				l1_width = l1_width > l2_width ? l1_width : l2_width;
 				l2_width = l2_width > l1_width ? l2_width : l1_width;
 
-				int l1 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\A")), l1_width);
-				int l2 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\B")), l2_width);
+				int l1 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\A")), l1_width);
+				int l2 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\B")), l2_width);
 				
 				++line_num;
 				std::string op = cell_type_translation.at(cell->type);
@@ -550,8 +550,8 @@ struct BtorDumper
 				l1_width = pow(2, ceil(log(l1_width)/log(2)));
 				int l2_width = 	cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
 				//assert(l2_width <= ceil(log(l1_width)/log(2)) );
-				int l1 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\A")), l1_width);
-				int l2 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\B")), ceil(log(l1_width)/log(2)));
+				int l1 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\A")), l1_width);
+				int l2 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\B")), ceil(log(l1_width)/log(2)));
 				int cell_output = ++line_num;
 				str = stringf ("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type).c_str(), l1_width, l1, l2);
 				fprintf(f, "%s\n", str.c_str());
@@ -559,7 +559,7 @@ struct BtorDumper
 				if(l2_width > ceil(log(l1_width)/log(2)))
 				{
 					int extra_width = l2_width - ceil(log(l1_width)/log(2));
-					l2 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\B")), l2_width);
+					l2 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\B")), l2_width);
 					++line_num;
 					str = stringf ("%d slice %d %d %d %d;6", line_num, extra_width, l2, l2_width-1, l2_width-extra_width);
 					fprintf(f, "%s\n", str.c_str());
@@ -592,8 +592,8 @@ struct BtorDumper
 				log("writing binary cell - %s\n", cstr(cell->type));
 				int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
 				log_assert(output_width == 1);
-				int l1 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\A")), output_width);
-				int l2 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\B")), output_width);
+				int l1 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\A")), output_width);
+				int l2 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\B")), output_width);
 				int l1_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
 				int l2_width = 	cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
 				if(l1_width >1)
@@ -628,9 +628,9 @@ struct BtorDumper
 			{
 				log("writing mux cell\n");
 				int output_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int();
-				int l1 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\A")), output_width);
-				int l2 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\B")), output_width);
-				int s = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\S")), 1);
+				int l1 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\A")), output_width);
+				int l2 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\B")), output_width);
+				int s = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\S")), 1);
 				++line_num;
 				str = stringf ("%d %s %d %d %d %d", 
 					line_num, cell_type_translation.at(cell->type).c_str(), output_width, s, l2, l1);//if s is 0 then l1, if s is 1 then l2 //according to the implementation of mux cell
@@ -644,10 +644,10 @@ struct BtorDumper
 				log("writing cell - %s\n", cstr(cell->type));
 				int output_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int();
 				log(" - width is %d\n", output_width);
-				int cond = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\CLK")), 1);
+				int cond = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\CLK")), 1);
 				bool polarity = cell->parameters.at(RTLIL::IdString("\\CLK_POLARITY")).as_bool();
-				const RTLIL::SigSpec* cell_output = &cell->connections_.at(RTLIL::IdString("\\Q"));
-				int value = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\D")), output_width);
+				const RTLIL::SigSpec* cell_output = &cell->connections().at(RTLIL::IdString("\\Q"));
+				int value = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\D")), output_width);
 				unsigned start_bit = 0;
 				for(unsigned i=0; i<cell_output->chunks().size(); ++i)
 				{
@@ -665,9 +665,9 @@ struct BtorDumper
 					}
 					if(cell->type == "$dffsr")
 					{
-						int sync_reset = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\CLR")), 1);
+						int sync_reset = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\CLR")), 1);
 						bool sync_reset_pol = cell->parameters.at(RTLIL::IdString("\\CLR_POLARITY")).as_bool();
-						int sync_reset_value = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\SET")),
+						int sync_reset_value = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\SET")),
 							output_width);
 						bool sync_reset_value_pol = cell->parameters.at(RTLIL::IdString("\\SET_POLARITY")).as_bool();
 						++line_num;
@@ -685,7 +685,7 @@ struct BtorDumper
 					int next = line_num;
 					if(cell->type == "$adff")
 					{
-						int async_reset = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\ARST")), 1);
+						int async_reset = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\ARST")), 1);
 						bool async_reset_pol = cell->parameters.at(RTLIL::IdString("\\ARST_POLARITY")).as_bool();
 						int async_reset_value = dump_const(&cell->parameters.at(RTLIL::IdString("\\ARST_VALUE")),
 							output_width, 0);
@@ -710,7 +710,7 @@ struct BtorDumper
 				str = cell->parameters.at(RTLIL::IdString("\\MEMID")).decode_string();
 				int mem = dump_memory(module->memories.at(RTLIL::IdString(str.c_str())));
 				int address_width = cell->parameters.at(RTLIL::IdString("\\ABITS")).as_int();
-				int address = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\ADDR")), address_width);
+				int address = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\ADDR")), address_width);
 				int data_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int();
 				++line_num;
 				str = stringf("%d read %d %d %d", line_num, data_width, mem, address);	
@@ -722,13 +722,13 @@ struct BtorDumper
 				log("writing memwr cell\n");
 				if (cell->parameters.at("\\CLK_ENABLE").as_bool() == false)
 					log_error("The btor backen does not support $memwr cells without built-in registers. Run memory_dff (but with -wr_only).\n");
-				int clk = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\CLK")), 1);
+				int clk = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\CLK")), 1);
 				bool polarity = cell->parameters.at(RTLIL::IdString("\\CLK_POLARITY")).as_bool();
-				int enable = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\EN")), 1);
+				int enable = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\EN")), 1);
 				int address_width = cell->parameters.at(RTLIL::IdString("\\ABITS")).as_int();
-				int address = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\ADDR")), address_width);
+				int address = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\ADDR")), address_width);
 				int data_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int();
-				int data = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\DATA")), data_width);
+				int data = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\DATA")), data_width);
 				str = cell->parameters.at(RTLIL::IdString("\\MEMID")).decode_string();
 				int mem = dump_memory(module->memories.at(RTLIL::IdString(str.c_str())));
 				++line_num;
@@ -757,11 +757,11 @@ struct BtorDumper
 			else if(cell->type == "$slice")
 			{
 				log("writing slice cell\n");
-				const RTLIL::SigSpec* input = &cell->connections_.at(RTLIL::IdString("\\A"));
+				const RTLIL::SigSpec* input = &cell->connections().at(RTLIL::IdString("\\A"));
 				int input_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
 				log_assert(input->size() == input_width);
 				int input_line = dump_sigspec(input, input_width);
-				const RTLIL::SigSpec* output = &cell->connections_.at(RTLIL::IdString("\\Y"));
+				const RTLIL::SigSpec* output = &cell->connections().at(RTLIL::IdString("\\Y"));
 				int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
 				log_assert(output->size() == output_width);
 				int offset = cell->parameters.at(RTLIL::IdString("\\OFFSET")).as_int();	
@@ -773,11 +773,11 @@ struct BtorDumper
 			else if(cell->type == "$concat")
 			{
 				log("writing concat cell\n");
-				const RTLIL::SigSpec* input_a = &cell->connections_.at(RTLIL::IdString("\\A"));
+				const RTLIL::SigSpec* input_a = &cell->connections().at(RTLIL::IdString("\\A"));
 				int input_a_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
 				log_assert(input_a->size() == input_a_width);
 				int input_a_line = dump_sigspec(input_a, input_a_width);
-				const RTLIL::SigSpec* input_b = &cell->connections_.at(RTLIL::IdString("\\B"));
+				const RTLIL::SigSpec* input_b = &cell->connections().at(RTLIL::IdString("\\B"));
 				int input_b_width = cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
 				log_assert(input_b->size() == input_b_width);
 				int input_b_line = dump_sigspec(input_b, input_b_width);
@@ -801,7 +801,7 @@ struct BtorDumper
 		RTLIL::SigSpec *output_sig = nullptr;
 		if (cell->type == "$memrd")
 		{
-			output_sig = &cell->connections_.at(RTLIL::IdString("\\DATA"));
+			output_sig = &cell->connections().at(RTLIL::IdString("\\DATA"));
 		}
 		else if(cell->type == "$memwr" || cell->type == "$assert")
 		{
@@ -809,11 +809,11 @@ struct BtorDumper
 		}
 		else if(cell->type == "$dff" || cell->type == "$adff" || cell->type == "$dffsr")
 		{
-			output_sig = &cell->connections_.at(RTLIL::IdString("\\Q"));
+			output_sig = &cell->connections().at(RTLIL::IdString("\\Q"));
 		}
 		else 
 		{
-			output_sig = &cell->connections_.at(RTLIL::IdString("\\Y"));
+			output_sig = &cell->connections().at(RTLIL::IdString("\\Y"));
 		}
 		return output_sig;
 	}
-- 
cgit v1.2.3


From f8fdc47d3361c1a3445a9357ca26cfe75907d6b0 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 26 Jul 2014 15:57:57 +0200
Subject: Manual fixes for new cell connections API

---
 backends/btor/btor.cc | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'backends/btor/btor.cc')

diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index 0316f7ab..bbfbc0f9 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -193,7 +193,7 @@ struct BtorDumper
 						break;
 					log(" -- found cell %s\n", cstr(cell_id));
 					RTLIL::Cell* cell = module->cells.at(cell_id);
-					RTLIL::SigSpec* cell_output = get_cell_output(cell);
+					const RTLIL::SigSpec* cell_output = get_cell_output(cell);
 					int cell_line = dump_cell(cell);				
 
 					if(dep_set.size()==1 && wire->width == cell_output->size())
@@ -796,9 +796,9 @@ struct BtorDumper
 		}
 	}
 
-	RTLIL::SigSpec* get_cell_output(RTLIL::Cell* cell)
+	const RTLIL::SigSpec* get_cell_output(RTLIL::Cell* cell)
 	{
-		RTLIL::SigSpec *output_sig = nullptr;
+		const RTLIL::SigSpec *output_sig = nullptr;
 		if (cell->type == "$memrd")
 		{
 			output_sig = &cell->connections().at(RTLIL::IdString("\\DATA"));
@@ -835,7 +835,7 @@ struct BtorDumper
 		for (auto it = module->cells.begin(); it != module->cells.end(); ++it)
 		{
 			RTLIL::Cell *cell = it->second;
-			RTLIL::SigSpec* output_sig = get_cell_output(cell);
+			const RTLIL::SigSpec* output_sig = get_cell_output(cell);
 			if(output_sig==nullptr)
 				continue;
 			RTLIL::SigSpec s = sigmap(*output_sig);
-- 
cgit v1.2.3


From 3f4e3ca8ad480c2e73e2072ada77078ffd95e08f Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 26 Jul 2014 16:14:02 +0200
Subject: More RTLIL::Cell API usage cleanups

---
 backends/btor/btor.cc | 68 +++++++++++++++++++++++++--------------------------
 1 file changed, 34 insertions(+), 34 deletions(-)

(limited to 'backends/btor/btor.cc')

diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index bbfbc0f9..f731e17e 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -387,8 +387,8 @@ struct BtorDumper
 			if(cell->type == "$assert")
 			{
 				log("writing assert cell - %s\n", cstr(cell->type));
-				const RTLIL::SigSpec* expr = &cell->connections().at(RTLIL::IdString("\\A"));
-				const RTLIL::SigSpec* en = &cell->connections().at(RTLIL::IdString("\\EN"));
+				const RTLIL::SigSpec* expr = &cell->get(RTLIL::IdString("\\A"));
+				const RTLIL::SigSpec* en = &cell->get(RTLIL::IdString("\\EN"));
 				log_assert(expr->size() == 1);
 				log_assert(en->size() == 1);
 				int expr_line = dump_sigspec(expr, 1);
@@ -420,7 +420,7 @@ struct BtorDumper
 				int w = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
 				int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
 				w = w>output_width ? w:output_width; //padding of w
-				int l = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\A")), w);				
+				int l = dump_sigspec(&cell->get(RTLIL::IdString("\\A")), w);				
 				int cell_line = l;
 				if(cell->type != "$pos")
 				{	
@@ -444,7 +444,7 @@ struct BtorDumper
 				int w = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
 				int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
 				log_assert(output_width == 1);
-				int l = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\A")), w);
+				int l = dump_sigspec(&cell->get(RTLIL::IdString("\\A")), w);
 				if(cell->type == "$logic_not" && w > 1)
 				{
 					++line_num;
@@ -481,8 +481,8 @@ struct BtorDumper
 				l1_width = l1_width > l2_width ? l1_width : l2_width;
 				l2_width = l2_width > l1_width ? l2_width : l1_width;
 
-				int l1 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\A")), l1_width);
-				int l2 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\B")), l2_width);
+				int l1 = dump_sigspec(&cell->get(RTLIL::IdString("\\A")), l1_width);
+				int l2 = dump_sigspec(&cell->get(RTLIL::IdString("\\B")), l2_width);
 				
 				++line_num;
 				std::string op = cell_type_translation.at(cell->type);
@@ -515,8 +515,8 @@ struct BtorDumper
 				l1_width = l1_width > l2_width ? l1_width : l2_width;
 				l2_width = l2_width > l1_width ? l2_width : l1_width;
 
-				int l1 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\A")), l1_width);
-				int l2 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\B")), l2_width);
+				int l1 = dump_sigspec(&cell->get(RTLIL::IdString("\\A")), l1_width);
+				int l2 = dump_sigspec(&cell->get(RTLIL::IdString("\\B")), l2_width);
 				
 				++line_num;
 				std::string op = cell_type_translation.at(cell->type);
@@ -550,8 +550,8 @@ struct BtorDumper
 				l1_width = pow(2, ceil(log(l1_width)/log(2)));
 				int l2_width = 	cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
 				//assert(l2_width <= ceil(log(l1_width)/log(2)) );
-				int l1 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\A")), l1_width);
-				int l2 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\B")), ceil(log(l1_width)/log(2)));
+				int l1 = dump_sigspec(&cell->get(RTLIL::IdString("\\A")), l1_width);
+				int l2 = dump_sigspec(&cell->get(RTLIL::IdString("\\B")), ceil(log(l1_width)/log(2)));
 				int cell_output = ++line_num;
 				str = stringf ("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type).c_str(), l1_width, l1, l2);
 				fprintf(f, "%s\n", str.c_str());
@@ -559,7 +559,7 @@ struct BtorDumper
 				if(l2_width > ceil(log(l1_width)/log(2)))
 				{
 					int extra_width = l2_width - ceil(log(l1_width)/log(2));
-					l2 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\B")), l2_width);
+					l2 = dump_sigspec(&cell->get(RTLIL::IdString("\\B")), l2_width);
 					++line_num;
 					str = stringf ("%d slice %d %d %d %d;6", line_num, extra_width, l2, l2_width-1, l2_width-extra_width);
 					fprintf(f, "%s\n", str.c_str());
@@ -592,8 +592,8 @@ struct BtorDumper
 				log("writing binary cell - %s\n", cstr(cell->type));
 				int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
 				log_assert(output_width == 1);
-				int l1 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\A")), output_width);
-				int l2 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\B")), output_width);
+				int l1 = dump_sigspec(&cell->get(RTLIL::IdString("\\A")), output_width);
+				int l2 = dump_sigspec(&cell->get(RTLIL::IdString("\\B")), output_width);
 				int l1_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
 				int l2_width = 	cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
 				if(l1_width >1)
@@ -628,9 +628,9 @@ struct BtorDumper
 			{
 				log("writing mux cell\n");
 				int output_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int();
-				int l1 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\A")), output_width);
-				int l2 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\B")), output_width);
-				int s = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\S")), 1);
+				int l1 = dump_sigspec(&cell->get(RTLIL::IdString("\\A")), output_width);
+				int l2 = dump_sigspec(&cell->get(RTLIL::IdString("\\B")), output_width);
+				int s = dump_sigspec(&cell->get(RTLIL::IdString("\\S")), 1);
 				++line_num;
 				str = stringf ("%d %s %d %d %d %d", 
 					line_num, cell_type_translation.at(cell->type).c_str(), output_width, s, l2, l1);//if s is 0 then l1, if s is 1 then l2 //according to the implementation of mux cell
@@ -644,10 +644,10 @@ struct BtorDumper
 				log("writing cell - %s\n", cstr(cell->type));
 				int output_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int();
 				log(" - width is %d\n", output_width);
-				int cond = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\CLK")), 1);
+				int cond = dump_sigspec(&cell->get(RTLIL::IdString("\\CLK")), 1);
 				bool polarity = cell->parameters.at(RTLIL::IdString("\\CLK_POLARITY")).as_bool();
-				const RTLIL::SigSpec* cell_output = &cell->connections().at(RTLIL::IdString("\\Q"));
-				int value = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\D")), output_width);
+				const RTLIL::SigSpec* cell_output = &cell->get(RTLIL::IdString("\\Q"));
+				int value = dump_sigspec(&cell->get(RTLIL::IdString("\\D")), output_width);
 				unsigned start_bit = 0;
 				for(unsigned i=0; i<cell_output->chunks().size(); ++i)
 				{
@@ -665,9 +665,9 @@ struct BtorDumper
 					}
 					if(cell->type == "$dffsr")
 					{
-						int sync_reset = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\CLR")), 1);
+						int sync_reset = dump_sigspec(&cell->get(RTLIL::IdString("\\CLR")), 1);
 						bool sync_reset_pol = cell->parameters.at(RTLIL::IdString("\\CLR_POLARITY")).as_bool();
-						int sync_reset_value = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\SET")),
+						int sync_reset_value = dump_sigspec(&cell->get(RTLIL::IdString("\\SET")),
 							output_width);
 						bool sync_reset_value_pol = cell->parameters.at(RTLIL::IdString("\\SET_POLARITY")).as_bool();
 						++line_num;
@@ -685,7 +685,7 @@ struct BtorDumper
 					int next = line_num;
 					if(cell->type == "$adff")
 					{
-						int async_reset = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\ARST")), 1);
+						int async_reset = dump_sigspec(&cell->get(RTLIL::IdString("\\ARST")), 1);
 						bool async_reset_pol = cell->parameters.at(RTLIL::IdString("\\ARST_POLARITY")).as_bool();
 						int async_reset_value = dump_const(&cell->parameters.at(RTLIL::IdString("\\ARST_VALUE")),
 							output_width, 0);
@@ -710,7 +710,7 @@ struct BtorDumper
 				str = cell->parameters.at(RTLIL::IdString("\\MEMID")).decode_string();
 				int mem = dump_memory(module->memories.at(RTLIL::IdString(str.c_str())));
 				int address_width = cell->parameters.at(RTLIL::IdString("\\ABITS")).as_int();
-				int address = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\ADDR")), address_width);
+				int address = dump_sigspec(&cell->get(RTLIL::IdString("\\ADDR")), address_width);
 				int data_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int();
 				++line_num;
 				str = stringf("%d read %d %d %d", line_num, data_width, mem, address);	
@@ -722,13 +722,13 @@ struct BtorDumper
 				log("writing memwr cell\n");
 				if (cell->parameters.at("\\CLK_ENABLE").as_bool() == false)
 					log_error("The btor backen does not support $memwr cells without built-in registers. Run memory_dff (but with -wr_only).\n");
-				int clk = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\CLK")), 1);
+				int clk = dump_sigspec(&cell->get(RTLIL::IdString("\\CLK")), 1);
 				bool polarity = cell->parameters.at(RTLIL::IdString("\\CLK_POLARITY")).as_bool();
-				int enable = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\EN")), 1);
+				int enable = dump_sigspec(&cell->get(RTLIL::IdString("\\EN")), 1);
 				int address_width = cell->parameters.at(RTLIL::IdString("\\ABITS")).as_int();
-				int address = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\ADDR")), address_width);
+				int address = dump_sigspec(&cell->get(RTLIL::IdString("\\ADDR")), address_width);
 				int data_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int();
-				int data = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\DATA")), data_width);
+				int data = dump_sigspec(&cell->get(RTLIL::IdString("\\DATA")), data_width);
 				str = cell->parameters.at(RTLIL::IdString("\\MEMID")).decode_string();
 				int mem = dump_memory(module->memories.at(RTLIL::IdString(str.c_str())));
 				++line_num;
@@ -757,11 +757,11 @@ struct BtorDumper
 			else if(cell->type == "$slice")
 			{
 				log("writing slice cell\n");
-				const RTLIL::SigSpec* input = &cell->connections().at(RTLIL::IdString("\\A"));
+				const RTLIL::SigSpec* input = &cell->get(RTLIL::IdString("\\A"));
 				int input_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
 				log_assert(input->size() == input_width);
 				int input_line = dump_sigspec(input, input_width);
-				const RTLIL::SigSpec* output = &cell->connections().at(RTLIL::IdString("\\Y"));
+				const RTLIL::SigSpec* output = &cell->get(RTLIL::IdString("\\Y"));
 				int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
 				log_assert(output->size() == output_width);
 				int offset = cell->parameters.at(RTLIL::IdString("\\OFFSET")).as_int();	
@@ -773,11 +773,11 @@ struct BtorDumper
 			else if(cell->type == "$concat")
 			{
 				log("writing concat cell\n");
-				const RTLIL::SigSpec* input_a = &cell->connections().at(RTLIL::IdString("\\A"));
+				const RTLIL::SigSpec* input_a = &cell->get(RTLIL::IdString("\\A"));
 				int input_a_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
 				log_assert(input_a->size() == input_a_width);
 				int input_a_line = dump_sigspec(input_a, input_a_width);
-				const RTLIL::SigSpec* input_b = &cell->connections().at(RTLIL::IdString("\\B"));
+				const RTLIL::SigSpec* input_b = &cell->get(RTLIL::IdString("\\B"));
 				int input_b_width = cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
 				log_assert(input_b->size() == input_b_width);
 				int input_b_line = dump_sigspec(input_b, input_b_width);
@@ -801,7 +801,7 @@ struct BtorDumper
 		const RTLIL::SigSpec *output_sig = nullptr;
 		if (cell->type == "$memrd")
 		{
-			output_sig = &cell->connections().at(RTLIL::IdString("\\DATA"));
+			output_sig = &cell->get(RTLIL::IdString("\\DATA"));
 		}
 		else if(cell->type == "$memwr" || cell->type == "$assert")
 		{
@@ -809,11 +809,11 @@ struct BtorDumper
 		}
 		else if(cell->type == "$dff" || cell->type == "$adff" || cell->type == "$dffsr")
 		{
-			output_sig = &cell->connections().at(RTLIL::IdString("\\Q"));
+			output_sig = &cell->get(RTLIL::IdString("\\Q"));
 		}
 		else 
 		{
-			output_sig = &cell->connections().at(RTLIL::IdString("\\Y"));
+			output_sig = &cell->get(RTLIL::IdString("\\Y"));
 		}
 		return output_sig;
 	}
-- 
cgit v1.2.3


From f9946232adf887e5aa4a48c64f88eaa17e424009 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 27 Jul 2014 01:49:51 +0200
Subject: Refactoring: Renamed RTLIL::Module::wires to wires_

---
 backends/btor/btor.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'backends/btor/btor.cc')

diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index f731e17e..f1e95ee1 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -80,7 +80,7 @@ struct BtorDumper
 	{
 		line_num=0;
 		str.clear();
-		for(auto it=module->wires.begin(); it!=module->wires.end(); ++it)
+		for(auto it=module->wires_.begin(); it!=module->wires_.end(); ++it)
 		{
 			if(it->second->port_input)
 			{
@@ -880,7 +880,7 @@ struct BtorDumper
 		std::map<int, RTLIL::Wire*> inputs, outputs;
 		std::vector<RTLIL::Wire*> safety;
 		
-		for (auto &wire_it : module->wires) {
+		for (auto &wire_it : module->wires_) {
 			RTLIL::Wire *wire = wire_it.second;
 			if (wire->port_input)
 				inputs[wire->port_id] = wire;
-- 
cgit v1.2.3


From 4c4b6021562c598c4510831bd547edaa97d14dac Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 27 Jul 2014 01:51:45 +0200
Subject: Refactoring: Renamed RTLIL::Module::cells to cells_

---
 backends/btor/btor.cc | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'backends/btor/btor.cc')

diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index f1e95ee1..ef0f0dd8 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -192,7 +192,7 @@ struct BtorDumper
 					if(cell_id == curr_cell)
 						break;
 					log(" -- found cell %s\n", cstr(cell_id));
-					RTLIL::Cell* cell = module->cells.at(cell_id);
+					RTLIL::Cell* cell = module->cells_.at(cell_id);
 					const RTLIL::SigSpec* cell_output = get_cell_output(cell);
 					int cell_line = dump_cell(cell);				
 
@@ -832,7 +832,7 @@ struct BtorDumper
 		
 		log("creating intermediate wires map\n");
 		//creating map of intermediate wires as output of some cell
-		for (auto it = module->cells.begin(); it != module->cells.end(); ++it)
+		for (auto it = module->cells_.begin(); it != module->cells_.end(); ++it)
 		{
 			RTLIL::Cell *cell = it->second;
 			const RTLIL::SigSpec* output_sig = get_cell_output(cell);
@@ -911,7 +911,7 @@ struct BtorDumper
 		}
 
 		log("writing cells\n");
-		for(auto cell_it = module->cells.begin(); cell_it != module->cells.end(); ++cell_it)
+		for(auto cell_it = module->cells_.begin(); cell_it != module->cells_.end(); ++cell_it)
 		{
 			dump_cell(cell_it->second);	
 		}
-- 
cgit v1.2.3


From 10e5791c5e5660cb784503d36439ee90d61eb06b Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 27 Jul 2014 10:18:00 +0200
Subject: Refactoring: Renamed RTLIL::Design::modules to modules_

---
 backends/btor/btor.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'backends/btor/btor.cc')

diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index ef0f0dd8..4af12100 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -964,7 +964,7 @@ struct BtorBackend : public Backend {
 		extra_args(f, filename, args, argidx);
 		
 		if (top_module_name.empty())
-			for (auto & mod_it:design->modules)
+			for (auto & mod_it:design->modules_)
 				if (mod_it.second->get_bool_attribute("\\top"))
 					top_module_name = mod_it.first;
 
@@ -975,7 +975,7 @@ struct BtorBackend : public Backend {
 		
 		std::vector<RTLIL::Module*> mod_list;
 
-		for (auto module_it : design->modules)
+		for (auto module_it : design->modules_)
 		{
 			RTLIL::Module *module = module_it.second;
 			if (module->get_bool_attribute("\\blackbox"))
-- 
cgit v1.2.3


From 7bd2d1064f2eceddc3c93c121c4154a2f594a040 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 28 Jul 2014 11:08:55 +0200
Subject: Using log_assert() instead of assert()

---
 backends/btor/btor.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'backends/btor/btor.cc')

diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index 4af12100..f721fdc9 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -549,7 +549,7 @@ struct BtorDumper
 				int l1_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
 				l1_width = pow(2, ceil(log(l1_width)/log(2)));
 				int l2_width = 	cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
-				//assert(l2_width <= ceil(log(l1_width)/log(2)) );
+				//log_assert(l2_width <= ceil(log(l1_width)/log(2)) );
 				int l1 = dump_sigspec(&cell->get(RTLIL::IdString("\\A")), l1_width);
 				int l2 = dump_sigspec(&cell->get(RTLIL::IdString("\\B")), ceil(log(l1_width)/log(2)));
 				int cell_output = ++line_num;
-- 
cgit v1.2.3


From 397b00252dc0c4af725614bd12fc299147ba8efa Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 29 Jul 2014 14:42:33 +0200
Subject: Added $shift and $shiftx cell types (needed for correct part select
 behavior)

---
 backends/btor/btor.cc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'backends/btor/btor.cc')

diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index f721fdc9..43c03669 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -111,6 +111,8 @@ struct BtorDumper
 		cell_type_translation["$shl"] = "sll";
 		cell_type_translation["$sshr"] = "sra";
 		cell_type_translation["$sshl"] = "sll";
+		cell_type_translation["$shift"] = "srl";
+		cell_type_translation["$shiftx"] = "srl";
 		cell_type_translation["$lt"] = "ult";
 		cell_type_translation["$le"] = "ulte";
 		cell_type_translation["$gt"] = "ugt";
@@ -540,7 +542,7 @@ struct BtorDumper
 				}
 				line_ref[cell->name]=line_num;
 			}
-			else if(cell->type == "$shr" || cell->type == "$shl" || cell->type == "$sshr" || cell->type == "$sshl")
+			else if(cell->type == "$shr" || cell->type == "$shl" || cell->type == "$sshr" || cell->type == "$sshl" || cell->type == "$shift" || cell->type == "$shiftx")
 			{
 				log("writing binary cell - %s\n", cstr(cell->type));
 				int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
-- 
cgit v1.2.3


From cdae8abe16847c533171fed111beea7b52202cce Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 31 Jul 2014 16:38:54 +0200
Subject: Renamed port access function on RTLIL::Cell, added param access
 functions

---
 backends/btor/btor.cc | 68 +++++++++++++++++++++++++--------------------------
 1 file changed, 34 insertions(+), 34 deletions(-)

(limited to 'backends/btor/btor.cc')

diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index 43c03669..d8a54234 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -389,8 +389,8 @@ struct BtorDumper
 			if(cell->type == "$assert")
 			{
 				log("writing assert cell - %s\n", cstr(cell->type));
-				const RTLIL::SigSpec* expr = &cell->get(RTLIL::IdString("\\A"));
-				const RTLIL::SigSpec* en = &cell->get(RTLIL::IdString("\\EN"));
+				const RTLIL::SigSpec* expr = &cell->getPort(RTLIL::IdString("\\A"));
+				const RTLIL::SigSpec* en = &cell->getPort(RTLIL::IdString("\\EN"));
 				log_assert(expr->size() == 1);
 				log_assert(en->size() == 1);
 				int expr_line = dump_sigspec(expr, 1);
@@ -422,7 +422,7 @@ struct BtorDumper
 				int w = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
 				int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
 				w = w>output_width ? w:output_width; //padding of w
-				int l = dump_sigspec(&cell->get(RTLIL::IdString("\\A")), w);				
+				int l = dump_sigspec(&cell->getPort(RTLIL::IdString("\\A")), w);				
 				int cell_line = l;
 				if(cell->type != "$pos")
 				{	
@@ -446,7 +446,7 @@ struct BtorDumper
 				int w = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
 				int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
 				log_assert(output_width == 1);
-				int l = dump_sigspec(&cell->get(RTLIL::IdString("\\A")), w);
+				int l = dump_sigspec(&cell->getPort(RTLIL::IdString("\\A")), w);
 				if(cell->type == "$logic_not" && w > 1)
 				{
 					++line_num;
@@ -483,8 +483,8 @@ struct BtorDumper
 				l1_width = l1_width > l2_width ? l1_width : l2_width;
 				l2_width = l2_width > l1_width ? l2_width : l1_width;
 
-				int l1 = dump_sigspec(&cell->get(RTLIL::IdString("\\A")), l1_width);
-				int l2 = dump_sigspec(&cell->get(RTLIL::IdString("\\B")), l2_width);
+				int l1 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\A")), l1_width);
+				int l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), l2_width);
 				
 				++line_num;
 				std::string op = cell_type_translation.at(cell->type);
@@ -517,8 +517,8 @@ struct BtorDumper
 				l1_width = l1_width > l2_width ? l1_width : l2_width;
 				l2_width = l2_width > l1_width ? l2_width : l1_width;
 
-				int l1 = dump_sigspec(&cell->get(RTLIL::IdString("\\A")), l1_width);
-				int l2 = dump_sigspec(&cell->get(RTLIL::IdString("\\B")), l2_width);
+				int l1 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\A")), l1_width);
+				int l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), l2_width);
 				
 				++line_num;
 				std::string op = cell_type_translation.at(cell->type);
@@ -552,8 +552,8 @@ struct BtorDumper
 				l1_width = pow(2, ceil(log(l1_width)/log(2)));
 				int l2_width = 	cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
 				//log_assert(l2_width <= ceil(log(l1_width)/log(2)) );
-				int l1 = dump_sigspec(&cell->get(RTLIL::IdString("\\A")), l1_width);
-				int l2 = dump_sigspec(&cell->get(RTLIL::IdString("\\B")), ceil(log(l1_width)/log(2)));
+				int l1 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\A")), l1_width);
+				int l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), ceil(log(l1_width)/log(2)));
 				int cell_output = ++line_num;
 				str = stringf ("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type).c_str(), l1_width, l1, l2);
 				fprintf(f, "%s\n", str.c_str());
@@ -561,7 +561,7 @@ struct BtorDumper
 				if(l2_width > ceil(log(l1_width)/log(2)))
 				{
 					int extra_width = l2_width - ceil(log(l1_width)/log(2));
-					l2 = dump_sigspec(&cell->get(RTLIL::IdString("\\B")), l2_width);
+					l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), l2_width);
 					++line_num;
 					str = stringf ("%d slice %d %d %d %d;6", line_num, extra_width, l2, l2_width-1, l2_width-extra_width);
 					fprintf(f, "%s\n", str.c_str());
@@ -594,8 +594,8 @@ struct BtorDumper
 				log("writing binary cell - %s\n", cstr(cell->type));
 				int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
 				log_assert(output_width == 1);
-				int l1 = dump_sigspec(&cell->get(RTLIL::IdString("\\A")), output_width);
-				int l2 = dump_sigspec(&cell->get(RTLIL::IdString("\\B")), output_width);
+				int l1 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\A")), output_width);
+				int l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), output_width);
 				int l1_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
 				int l2_width = 	cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
 				if(l1_width >1)
@@ -630,9 +630,9 @@ struct BtorDumper
 			{
 				log("writing mux cell\n");
 				int output_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int();
-				int l1 = dump_sigspec(&cell->get(RTLIL::IdString("\\A")), output_width);
-				int l2 = dump_sigspec(&cell->get(RTLIL::IdString("\\B")), output_width);
-				int s = dump_sigspec(&cell->get(RTLIL::IdString("\\S")), 1);
+				int l1 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\A")), output_width);
+				int l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), output_width);
+				int s = dump_sigspec(&cell->getPort(RTLIL::IdString("\\S")), 1);
 				++line_num;
 				str = stringf ("%d %s %d %d %d %d", 
 					line_num, cell_type_translation.at(cell->type).c_str(), output_width, s, l2, l1);//if s is 0 then l1, if s is 1 then l2 //according to the implementation of mux cell
@@ -646,10 +646,10 @@ struct BtorDumper
 				log("writing cell - %s\n", cstr(cell->type));
 				int output_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int();
 				log(" - width is %d\n", output_width);
-				int cond = dump_sigspec(&cell->get(RTLIL::IdString("\\CLK")), 1);
+				int cond = dump_sigspec(&cell->getPort(RTLIL::IdString("\\CLK")), 1);
 				bool polarity = cell->parameters.at(RTLIL::IdString("\\CLK_POLARITY")).as_bool();
-				const RTLIL::SigSpec* cell_output = &cell->get(RTLIL::IdString("\\Q"));
-				int value = dump_sigspec(&cell->get(RTLIL::IdString("\\D")), output_width);
+				const RTLIL::SigSpec* cell_output = &cell->getPort(RTLIL::IdString("\\Q"));
+				int value = dump_sigspec(&cell->getPort(RTLIL::IdString("\\D")), output_width);
 				unsigned start_bit = 0;
 				for(unsigned i=0; i<cell_output->chunks().size(); ++i)
 				{
@@ -667,9 +667,9 @@ struct BtorDumper
 					}
 					if(cell->type == "$dffsr")
 					{
-						int sync_reset = dump_sigspec(&cell->get(RTLIL::IdString("\\CLR")), 1);
+						int sync_reset = dump_sigspec(&cell->getPort(RTLIL::IdString("\\CLR")), 1);
 						bool sync_reset_pol = cell->parameters.at(RTLIL::IdString("\\CLR_POLARITY")).as_bool();
-						int sync_reset_value = dump_sigspec(&cell->get(RTLIL::IdString("\\SET")),
+						int sync_reset_value = dump_sigspec(&cell->getPort(RTLIL::IdString("\\SET")),
 							output_width);
 						bool sync_reset_value_pol = cell->parameters.at(RTLIL::IdString("\\SET_POLARITY")).as_bool();
 						++line_num;
@@ -687,7 +687,7 @@ struct BtorDumper
 					int next = line_num;
 					if(cell->type == "$adff")
 					{
-						int async_reset = dump_sigspec(&cell->get(RTLIL::IdString("\\ARST")), 1);
+						int async_reset = dump_sigspec(&cell->getPort(RTLIL::IdString("\\ARST")), 1);
 						bool async_reset_pol = cell->parameters.at(RTLIL::IdString("\\ARST_POLARITY")).as_bool();
 						int async_reset_value = dump_const(&cell->parameters.at(RTLIL::IdString("\\ARST_VALUE")),
 							output_width, 0);
@@ -712,7 +712,7 @@ struct BtorDumper
 				str = cell->parameters.at(RTLIL::IdString("\\MEMID")).decode_string();
 				int mem = dump_memory(module->memories.at(RTLIL::IdString(str.c_str())));
 				int address_width = cell->parameters.at(RTLIL::IdString("\\ABITS")).as_int();
-				int address = dump_sigspec(&cell->get(RTLIL::IdString("\\ADDR")), address_width);
+				int address = dump_sigspec(&cell->getPort(RTLIL::IdString("\\ADDR")), address_width);
 				int data_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int();
 				++line_num;
 				str = stringf("%d read %d %d %d", line_num, data_width, mem, address);	
@@ -724,13 +724,13 @@ struct BtorDumper
 				log("writing memwr cell\n");
 				if (cell->parameters.at("\\CLK_ENABLE").as_bool() == false)
 					log_error("The btor backen does not support $memwr cells without built-in registers. Run memory_dff (but with -wr_only).\n");
-				int clk = dump_sigspec(&cell->get(RTLIL::IdString("\\CLK")), 1);
+				int clk = dump_sigspec(&cell->getPort(RTLIL::IdString("\\CLK")), 1);
 				bool polarity = cell->parameters.at(RTLIL::IdString("\\CLK_POLARITY")).as_bool();
-				int enable = dump_sigspec(&cell->get(RTLIL::IdString("\\EN")), 1);
+				int enable = dump_sigspec(&cell->getPort(RTLIL::IdString("\\EN")), 1);
 				int address_width = cell->parameters.at(RTLIL::IdString("\\ABITS")).as_int();
-				int address = dump_sigspec(&cell->get(RTLIL::IdString("\\ADDR")), address_width);
+				int address = dump_sigspec(&cell->getPort(RTLIL::IdString("\\ADDR")), address_width);
 				int data_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int();
-				int data = dump_sigspec(&cell->get(RTLIL::IdString("\\DATA")), data_width);
+				int data = dump_sigspec(&cell->getPort(RTLIL::IdString("\\DATA")), data_width);
 				str = cell->parameters.at(RTLIL::IdString("\\MEMID")).decode_string();
 				int mem = dump_memory(module->memories.at(RTLIL::IdString(str.c_str())));
 				++line_num;
@@ -759,11 +759,11 @@ struct BtorDumper
 			else if(cell->type == "$slice")
 			{
 				log("writing slice cell\n");
-				const RTLIL::SigSpec* input = &cell->get(RTLIL::IdString("\\A"));
+				const RTLIL::SigSpec* input = &cell->getPort(RTLIL::IdString("\\A"));
 				int input_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
 				log_assert(input->size() == input_width);
 				int input_line = dump_sigspec(input, input_width);
-				const RTLIL::SigSpec* output = &cell->get(RTLIL::IdString("\\Y"));
+				const RTLIL::SigSpec* output = &cell->getPort(RTLIL::IdString("\\Y"));
 				int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
 				log_assert(output->size() == output_width);
 				int offset = cell->parameters.at(RTLIL::IdString("\\OFFSET")).as_int();	
@@ -775,11 +775,11 @@ struct BtorDumper
 			else if(cell->type == "$concat")
 			{
 				log("writing concat cell\n");
-				const RTLIL::SigSpec* input_a = &cell->get(RTLIL::IdString("\\A"));
+				const RTLIL::SigSpec* input_a = &cell->getPort(RTLIL::IdString("\\A"));
 				int input_a_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
 				log_assert(input_a->size() == input_a_width);
 				int input_a_line = dump_sigspec(input_a, input_a_width);
-				const RTLIL::SigSpec* input_b = &cell->get(RTLIL::IdString("\\B"));
+				const RTLIL::SigSpec* input_b = &cell->getPort(RTLIL::IdString("\\B"));
 				int input_b_width = cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
 				log_assert(input_b->size() == input_b_width);
 				int input_b_line = dump_sigspec(input_b, input_b_width);
@@ -803,7 +803,7 @@ struct BtorDumper
 		const RTLIL::SigSpec *output_sig = nullptr;
 		if (cell->type == "$memrd")
 		{
-			output_sig = &cell->get(RTLIL::IdString("\\DATA"));
+			output_sig = &cell->getPort(RTLIL::IdString("\\DATA"));
 		}
 		else if(cell->type == "$memwr" || cell->type == "$assert")
 		{
@@ -811,11 +811,11 @@ struct BtorDumper
 		}
 		else if(cell->type == "$dff" || cell->type == "$adff" || cell->type == "$dffsr")
 		{
-			output_sig = &cell->get(RTLIL::IdString("\\Q"));
+			output_sig = &cell->getPort(RTLIL::IdString("\\Q"));
 		}
 		else 
 		{
-			output_sig = &cell->get(RTLIL::IdString("\\Y"));
+			output_sig = &cell->getPort(RTLIL::IdString("\\Y"));
 		}
 		return output_sig;
 	}
-- 
cgit v1.2.3


From b9bd22b8c8d46284fba4d4c1cbd09092a9ccc5c3 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 2 Aug 2014 13:11:01 +0200
Subject: More cleanups related to RTLIL::IdString usage

---
 backends/btor/btor.cc | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

(limited to 'backends/btor/btor.cc')

diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index d8a54234..201be0cf 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -428,7 +428,7 @@ struct BtorDumper
 				{	
 					cell_line = ++line_num;
 					bool reduced = (cell->type == "$not" || cell->type == "$neg") ? false : true;
-					str = stringf ("%d %s %d %d", cell_line, cell_type_translation.at(cell->type).c_str(), reduced?output_width:w, l);
+					str = stringf ("%d %s %d %d", cell_line, cell_type_translation.at(cell->type.str()).c_str(), reduced?output_width:w, l);
 					fprintf(f, "%s\n", str.c_str());
 				}
 				if(output_width < w && (cell->type == "$not" || cell->type == "$neg" || cell->type == "$pos"))
@@ -487,13 +487,13 @@ struct BtorDumper
 				int l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), l2_width);
 				
 				++line_num;
-				std::string op = cell_type_translation.at(cell->type);
+				std::string op = cell_type_translation.at(cell->type.str());
 				if(cell->type == "$lt" || cell->type == "$le" ||
 				 cell->type == "$eq" || cell->type == "$ne" || cell->type == "$eqx" || cell->type == "$nex" ||
 				 cell->type == "$ge" || cell->type == "$gt")
 				{
 					if(l1_signed)
-						op = s_cell_type_translation.at(cell->type);
+						op = s_cell_type_translation.at(cell->type.str());
 				}
 				
 				str = stringf ("%d %s %d %d %d", line_num, op.c_str(), output_width, l1, l2);
@@ -521,9 +521,9 @@ struct BtorDumper
 				int l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), l2_width);
 				
 				++line_num;
-				std::string op = cell_type_translation.at(cell->type);
+				std::string op = cell_type_translation.at(cell->type.str());
 				if(cell->type == "$div" && l1_signed)
-					op = s_cell_type_translation.at(cell->type);
+					op = s_cell_type_translation.at(cell->type.str());
 				else if(cell->type == "$mod")
 				{
 					if(l1_signed)
@@ -555,7 +555,7 @@ struct BtorDumper
 				int l1 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\A")), l1_width);
 				int l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), ceil(log(l1_width)/log(2)));
 				int cell_output = ++line_num;
-				str = stringf ("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type).c_str(), l1_width, l1, l2);
+				str = stringf ("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type.str()).c_str(), l1_width, l1, l2);
 				fprintf(f, "%s\n", str.c_str());
 
 				if(l2_width > ceil(log(l1_width)/log(2)))
@@ -635,7 +635,7 @@ struct BtorDumper
 				int s = dump_sigspec(&cell->getPort(RTLIL::IdString("\\S")), 1);
 				++line_num;
 				str = stringf ("%d %s %d %d %d %d", 
-					line_num, cell_type_translation.at(cell->type).c_str(), output_width, s, l2, l1);//if s is 0 then l1, if s is 1 then l2 //according to the implementation of mux cell
+					line_num, cell_type_translation.at(cell->type.str()).c_str(), output_width, s, l2, l1);//if s is 0 then l1, if s is 1 then l2 //according to the implementation of mux cell
 				fprintf(f, "%s\n", str.c_str());
 				line_ref[cell->name]=line_num;
 			}
@@ -697,7 +697,7 @@ struct BtorDumper
 						fprintf(f, "%s\n", str.c_str());
 					}
 					++line_num;
-					str = stringf ("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type).c_str(), 
+					str = stringf ("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type.str()).c_str(), 
 						output_width, reg, next);
 					fprintf(f, "%s\n", str.c_str());
 				}
@@ -768,7 +768,7 @@ struct BtorDumper
 				log_assert(output->size() == output_width);
 				int offset = cell->parameters.at(RTLIL::IdString("\\OFFSET")).as_int();	
 				++line_num;
-				str = stringf("%d %s %d %d %d %d", line_num, cell_type_translation.at(cell->type).c_str(), output_width, input_line, output_width+offset-1, offset);	
+				str = stringf("%d %s %d %d %d %d", line_num, cell_type_translation.at(cell->type.str()).c_str(), output_width, input_line, output_width+offset-1, offset);
 				fprintf(f, "%s\n", str.c_str());				
 				line_ref[cell->name]=line_num;	
 			}
@@ -784,7 +784,7 @@ struct BtorDumper
 				log_assert(input_b->size() == input_b_width);
 				int input_b_line = dump_sigspec(input_b, input_b_width);
 				++line_num;
-				str = stringf("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type).c_str(), input_a_width+input_b_width, 
+				str = stringf("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type.str()).c_str(), input_a_width+input_b_width, 
 					input_a_line, input_b_line);	
 				fprintf(f, "%s\n", str.c_str());				
 				line_ref[cell->name]=line_num;				
@@ -888,7 +888,7 @@ struct BtorDumper
 				inputs[wire->port_id] = wire;
 			if (wire->port_output) {
 				outputs[wire->port_id] = wire;
-				if (wire->name.find("safety") != std::string::npos )
+				if (wire->name.str().find("safety") != std::string::npos )
 					safety.push_back(wire);
 			}
 		}
-- 
cgit v1.2.3


From 04727c7e0fb4c00b38999da192e4ada2a6f9474a Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 2 Aug 2014 18:58:40 +0200
Subject: No implicit conversion from IdString to anything else

---
 backends/btor/btor.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'backends/btor/btor.cc')

diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index 201be0cf..a81d8f15 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -968,7 +968,7 @@ struct BtorBackend : public Backend {
 		if (top_module_name.empty())
 			for (auto & mod_it:design->modules_)
 				if (mod_it.second->get_bool_attribute("\\top"))
-					top_module_name = mod_it.first;
+					top_module_name = mod_it.first.str();
 
 		fprintf(f, "; Generated by %s\n", yosys_version_str);
 		fprintf(f, ";  %s developed and maintained by Clifford Wolf <clifford@clifford.at>\n", yosys_version_str);
-- 
cgit v1.2.3


From 5dce303a2a2c27d50e99856b6f33467798e13020 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 23 Aug 2014 13:54:21 +0200
Subject: Changed backend-api from FILE to std::ostream

---
 backends/btor/btor.cc | 130 +++++++++++++++++++++++++-------------------------
 1 file changed, 65 insertions(+), 65 deletions(-)

(limited to 'backends/btor/btor.cc')

diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index a81d8f15..9b770518 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -60,7 +60,7 @@ struct WireInfoOrder
 
 struct BtorDumper
 {
-	FILE *f;
+	std::ostream &f;
 	RTLIL::Module *module;
 	RTLIL::Design *design;
 	BtorDumperConfig *config;
@@ -75,7 +75,7 @@ struct BtorDumper
 	std::map<RTLIL::IdString, bool> basic_wires;//input wires and registers	
 	RTLIL::IdString curr_cell; //current cell being dumped
 	std::map<std::string, std::string> cell_type_translation, s_cell_type_translation; //RTLIL to BTOR translation
-	BtorDumper(FILE *f, RTLIL::Module *module, RTLIL::Design *design, BtorDumperConfig *config) :
+	BtorDumper(std::ostream &f, RTLIL::Module *module, RTLIL::Design *design, BtorDumperConfig *config) :
 			f(f), module(module), design(design), config(config), ct(design), sigmap(module)
 	{
 		line_num=0;
@@ -174,7 +174,7 @@ struct BtorDumper
 				++line_num;
 				line_ref[wire->name]=line_num;			
 				str = stringf("%d var %d %s", line_num, wire->width, cstr(wire->name));
-				fprintf(f, "%s\n", str.c_str());
+				f << stringf("%s\n", str.c_str());
 				return line_num;
 			}
 			else return it->second;
@@ -216,13 +216,13 @@ struct BtorDumper
 								wire_line = ++line_num;
 								str = stringf("%d slice %d %d %d %d;1", line_num, cell_output->chunks().at(j).width,
 									cell_line, start_bit-1, start_bit-cell_output->chunks().at(j).width);
-								fprintf(f, "%s\n", str.c_str());
+								f << stringf("%s\n", str.c_str());
 								wire_width += cell_output->chunks().at(j).width;
 								if(prev_wire_line!=0)
 								{
 									++line_num;
 									str = stringf("%d concat %d %d %d", line_num, wire_width, wire_line, prev_wire_line);
-									fprintf(f, "%s\n", str.c_str());
+									f << stringf("%s\n", str.c_str());
 									wire_line = line_num;
 								}
 							}
@@ -259,7 +259,7 @@ struct BtorDumper
 			int address_bits = ceil(log(memory->size)/log(2));
 			str = stringf("%d array %d %d", line_num, memory->width, address_bits);
 			line_ref[memory->name]=line_num;			
-			fprintf(f, "%s\n", str.c_str());
+			f << stringf("%s\n", str.c_str());
 			return line_num;
 		}
 		else return it->second;
@@ -279,7 +279,7 @@ struct BtorDumper
 
 			++line_num;
 			str = stringf("%d const %d %s", line_num, width, data_str.c_str());
-			fprintf(f, "%s\n", str.c_str());
+			f << stringf("%s\n", str.c_str());
 			return line_num;
 		}
 		else
@@ -307,7 +307,7 @@ struct BtorDumper
 				++line_num;
 				str = stringf("%d slice %d %d %d %d;2", line_num, chunk->width, wire_line_num, 
 					chunk->width + chunk->offset - 1, chunk->offset);
-				fprintf(f, "%s\n", str.c_str());
+				f << stringf("%s\n", str.c_str());
 				l = line_num;				 
 			}
 		}
@@ -339,7 +339,7 @@ struct BtorDumper
 					w2 = s.chunks().at(i).width;
 					++line_num;
 					str = stringf("%d concat %d %d %d", line_num, w1+w2, l2, l1);
-					fprintf(f, "%s\n", str.c_str());
+					f << stringf("%s\n", str.c_str());
 					l1=line_num;
 					w1+=w2;
 				}
@@ -361,17 +361,17 @@ struct BtorDumper
 				//TODO: case the signal is signed
 				++line_num;
 				str = stringf ("%d zero %d", line_num, expected_width - s.size());
-				fprintf(f, "%s\n", str.c_str());
+				f << stringf("%s\n", str.c_str());
 				++line_num;
 				str = stringf ("%d concat %d %d %d", line_num, expected_width, line_num-1, l);
-				fprintf(f, "%s\n", str.c_str());
+				f << stringf("%s\n", str.c_str());
 				l = line_num;
 			}
 			else if(expected_width < s.size())
 			{
 				++line_num;
 				str = stringf ("%d slice %d %d %d %d;3", line_num, expected_width, l, expected_width-1, 0);
-				fprintf(f, "%s\n", str.c_str());
+				f << stringf("%s\n", str.c_str());
 				l = line_num;
 			}
 		}
@@ -397,21 +397,21 @@ struct BtorDumper
 				int en_line = dump_sigspec(en, 1);
 				int one_line = ++line_num;
 				str = stringf("%d one 1", line_num);
-				fprintf(f, "%s\n", str.c_str());
+				f << stringf("%s\n", str.c_str());
 				++line_num;
 				str = stringf("%d %s %d %d %d", line_num, cell_type_translation.at("$eq").c_str(), 1, en_line, one_line);
-				fprintf(f, "%s\n", str.c_str());
+				f << stringf("%s\n", str.c_str());
 				++line_num;
 				str = stringf("%d %s %d %d %d %d", line_num, cell_type_translation.at("$mux").c_str(), 1, line_num-1,
 					expr_line, one_line);
-				fprintf(f, "%s\n", str.c_str());
+				f << stringf("%s\n", str.c_str());
 				int cell_line = ++line_num;
 				str = stringf("%d %s %d %d", line_num, cell_type_translation.at("$assert").c_str(), 1, -1*(line_num-1));
 				//multiplying the line number with -1, which means logical negation
 				//the reason for negative sign is that the properties in btor are given as "negation of the original property"
 				//bug identified by bobosoft
 				//http://www.reddit.com/r/yosys/comments/1w3xig/btor_backend_bug/
-				fprintf(f, "%s\n", str.c_str());
+				f << stringf("%s\n", str.c_str());
 				line_ref[cell->name]=cell_line;
 			}
 			//unary cells
@@ -429,13 +429,13 @@ struct BtorDumper
 					cell_line = ++line_num;
 					bool reduced = (cell->type == "$not" || cell->type == "$neg") ? false : true;
 					str = stringf ("%d %s %d %d", cell_line, cell_type_translation.at(cell->type.str()).c_str(), reduced?output_width:w, l);
-					fprintf(f, "%s\n", str.c_str());
+					f << stringf("%s\n", str.c_str());
 				}
 				if(output_width < w && (cell->type == "$not" || cell->type == "$neg" || cell->type == "$pos"))
 				{
 					++line_num;
 					str = stringf ("%d slice %d %d %d %d;4", line_num, output_width, cell_line, output_width-1, 0);
-					fprintf(f, "%s\n", str.c_str());
+					f << stringf("%s\n", str.c_str());
 					cell_line = line_num;
 				}				
 				line_ref[cell->name]=cell_line;
@@ -451,17 +451,17 @@ struct BtorDumper
 				{
 					++line_num;
 					str = stringf ("%d %s %d %d", line_num, cell_type_translation.at("$reduce_or").c_str(), output_width, l);
-					fprintf(f, "%s\n", str.c_str());
+					f << stringf("%s\n", str.c_str());
 				}
 				else if(cell->type == "$reduce_xnor")
 				{
 					++line_num;
 					str = stringf ("%d %s %d %d", line_num, cell_type_translation.at("$reduce_xor").c_str(), output_width, l);
-					fprintf(f, "%s\n", str.c_str());
+					f << stringf("%s\n", str.c_str());
 				}		
 				++line_num;
 				str = stringf ("%d %s %d %d", line_num, cell_type_translation.at("$not").c_str(), output_width, line_num-1);
-				fprintf(f, "%s\n", str.c_str());
+				f << stringf("%s\n", str.c_str());
 				line_ref[cell->name]=line_num;
 			}
 			//binary cells
@@ -497,7 +497,7 @@ struct BtorDumper
 				}
 				
 				str = stringf ("%d %s %d %d %d", line_num, op.c_str(), output_width, l1, l2);
-				fprintf(f, "%s\n", str.c_str());
+				f << stringf("%s\n", str.c_str());
 
 				line_ref[cell->name]=line_num;
 			}
@@ -532,13 +532,13 @@ struct BtorDumper
 						op = s_cell_type_translation.at("$mody");
 				}
 				str = stringf ("%d %s %d %d %d", line_num, op.c_str(), l1_width, l1, l2);
-				fprintf(f, "%s\n", str.c_str());
+				f << stringf("%s\n", str.c_str());
 
 				if(output_width < l1_width)
 				{
 					++line_num;
 					str = stringf ("%d slice %d %d %d %d;5", line_num, output_width, line_num-1, output_width-1, 0);
-					fprintf(f, "%s\n", str.c_str());
+					f << stringf("%s\n", str.c_str());
 				}
 				line_ref[cell->name]=line_num;
 			}
@@ -556,7 +556,7 @@ struct BtorDumper
 				int l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), ceil(log(l1_width)/log(2)));
 				int cell_output = ++line_num;
 				str = stringf ("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type.str()).c_str(), l1_width, l1, l2);
-				fprintf(f, "%s\n", str.c_str());
+				f << stringf("%s\n", str.c_str());
 
 				if(l2_width > ceil(log(l1_width)/log(2)))
 				{
@@ -564,19 +564,19 @@ struct BtorDumper
 					l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), l2_width);
 					++line_num;
 					str = stringf ("%d slice %d %d %d %d;6", line_num, extra_width, l2, l2_width-1, l2_width-extra_width);
-					fprintf(f, "%s\n", str.c_str());
+					f << stringf("%s\n", str.c_str());
 					++line_num;
 					str = stringf ("%d one %d", line_num, extra_width);
-					fprintf(f, "%s\n", str.c_str());
+					f << stringf("%s\n", str.c_str());
 					int mux = ++line_num;
 					str = stringf ("%d %s %d %d %d", line_num, cell_type_translation.at("$gt").c_str(), 1, line_num-2, line_num-1);
-					fprintf(f, "%s\n", str.c_str());
+					f << stringf("%s\n", str.c_str());
 					++line_num;
 					str = stringf("%d %s %d", line_num, l1_signed && cell->type == "$sshr" ? "ones":"zero", l1_width);
-					fprintf(f, "%s\n", str.c_str());
+					f << stringf("%s\n", str.c_str());
 					++line_num;
 					str = stringf ("%d %s %d %d %d %d", line_num, cell_type_translation.at("$mux").c_str(), l1_width, mux, line_num-1, cell_output);
-					fprintf(f, "%s\n", str.c_str());
+					f << stringf("%s\n", str.c_str());
 					cell_output = line_num;
 				}
 
@@ -584,7 +584,7 @@ struct BtorDumper
 				{
 					++line_num;
 					str = stringf ("%d slice %d %d %d %d;5", line_num, output_width, cell_output, output_width-1, 0);
-					fprintf(f, "%s\n", str.c_str());
+					f << stringf("%s\n", str.c_str());
 					cell_output = line_num;
 				}
 				line_ref[cell->name] = cell_output;	
@@ -602,14 +602,14 @@ struct BtorDumper
 				{
 					++line_num;
 					str = stringf ("%d %s %d %d", line_num, cell_type_translation.at("$reduce_or").c_str(), output_width, l1);
-					fprintf(f, "%s\n", str.c_str());
+					f << stringf("%s\n", str.c_str());
 					l1 = line_num;
 				}
 				if(l2_width > 1)
 				{
 					++line_num;
 					str = stringf ("%d %s %d %d", line_num, cell_type_translation.at("$reduce_or").c_str(), output_width, l2);
-					fprintf(f, "%s\n", str.c_str());
+					f << stringf("%s\n", str.c_str());
 					l2 = line_num;
 				}
 				if(cell->type == "$logic_and")
@@ -622,7 +622,7 @@ struct BtorDumper
 					++line_num;
 					str = stringf ("%d %s %d %d %d", line_num, cell_type_translation.at("$or").c_str(), output_width, l1, l2);
 				}
-				fprintf(f, "%s\n", str.c_str());
+				f << stringf("%s\n", str.c_str());
 				line_ref[cell->name]=line_num;
 			}
 			//multiplexers
@@ -636,7 +636,7 @@ struct BtorDumper
 				++line_num;
 				str = stringf ("%d %s %d %d %d %d", 
 					line_num, cell_type_translation.at(cell->type.str()).c_str(), output_width, s, l2, l1);//if s is 0 then l1, if s is 1 then l2 //according to the implementation of mux cell
-				fprintf(f, "%s\n", str.c_str());
+				f << stringf("%s\n", str.c_str());
 				line_ref[cell->name]=line_num;
 			}
 			//registers
@@ -663,7 +663,7 @@ struct BtorDumper
 						slice = ++line_num;
 						str = stringf ("%d slice %d %d %d %d;", line_num, output_width, value, start_bit-1, 
 							start_bit-output_width);
-						fprintf(f, "%s\n", str.c_str());
+						f << stringf("%s\n", str.c_str());
 					}
 					if(cell->type == "$dffsr")
 					{
@@ -676,14 +676,14 @@ struct BtorDumper
 						str = stringf ("%d %s %d %s%d %s%d %d", line_num, cell_type_translation.at("$mux").c_str(), 
 							output_width, sync_reset_pol ? "":"-", sync_reset, sync_reset_value_pol? "":"-", 
 							sync_reset_value, slice);
-						fprintf(f, "%s\n", str.c_str());
+						f << stringf("%s\n", str.c_str());
 						slice = line_num;
 					}
 					++line_num;
 					str = stringf ("%d %s %d %s%d %d %d", line_num, cell_type_translation.at("$mux").c_str(), 
 						output_width, polarity?"":"-", cond, slice, reg);
 				
-					fprintf(f, "%s\n", str.c_str());
+					f << stringf("%s\n", str.c_str());
 					int next = line_num;
 					if(cell->type == "$adff")
 					{
@@ -694,12 +694,12 @@ struct BtorDumper
 						++line_num;
 						str = stringf ("%d %s %d %s%d %d %d", line_num, cell_type_translation.at("$mux").c_str(), 
 							output_width, async_reset_pol ? "":"-", async_reset, async_reset_value, next);
-						fprintf(f, "%s\n", str.c_str());
+						f << stringf("%s\n", str.c_str());
 					}
 					++line_num;
 					str = stringf ("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type.str()).c_str(), 
 						output_width, reg, next);
-					fprintf(f, "%s\n", str.c_str());
+					f << stringf("%s\n", str.c_str());
 				}
 				line_ref[cell->name]=line_num;
 			}
@@ -716,7 +716,7 @@ struct BtorDumper
 				int data_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int();
 				++line_num;
 				str = stringf("%d read %d %d %d", line_num, data_width, mem, address);	
-				fprintf(f, "%s\n", str.c_str());
+				f << stringf("%s\n", str.c_str());
 				line_ref[cell->name]=line_num;
 			}
 			else if(cell->type == "$memwr")
@@ -738,22 +738,22 @@ struct BtorDumper
 					str = stringf("%d one 1", line_num);
 				else
 					str = stringf("%d zero 1", line_num);
-				fprintf(f, "%s\n", str.c_str());
+				f << stringf("%s\n", str.c_str());
 				++line_num;
 				str = stringf("%d eq 1 %d %d", line_num, clk, line_num-1);	
-				fprintf(f, "%s\n", str.c_str());
+				f << stringf("%s\n", str.c_str());
 				++line_num;
 				str = stringf("%d and 1 %d %d", line_num, line_num-1, enable);	
-				fprintf(f, "%s\n", str.c_str());
+				f << stringf("%s\n", str.c_str());
 				++line_num;
 				str = stringf("%d write %d %d %d %d %d", line_num, data_width, address_width, mem, address, data);	
-				fprintf(f, "%s\n", str.c_str());
+				f << stringf("%s\n", str.c_str());
 				++line_num;
 				str = stringf("%d acond %d %d %d %d %d", line_num, data_width, address_width, line_num-2/*enable*/, line_num-1, mem);	
-				fprintf(f, "%s\n", str.c_str());				
+				f << stringf("%s\n", str.c_str());				
 				++line_num;
 				str = stringf("%d anext %d %d %d %d", line_num, data_width, address_width, mem, line_num-1);	
-				fprintf(f, "%s\n", str.c_str());				
+				f << stringf("%s\n", str.c_str());				
 				line_ref[cell->name]=line_num;
 			}
 			else if(cell->type == "$slice")
@@ -769,7 +769,7 @@ struct BtorDumper
 				int offset = cell->parameters.at(RTLIL::IdString("\\OFFSET")).as_int();	
 				++line_num;
 				str = stringf("%d %s %d %d %d %d", line_num, cell_type_translation.at(cell->type.str()).c_str(), output_width, input_line, output_width+offset-1, offset);
-				fprintf(f, "%s\n", str.c_str());				
+				f << stringf("%s\n", str.c_str());				
 				line_ref[cell->name]=line_num;	
 			}
 			else if(cell->type == "$concat")
@@ -786,7 +786,7 @@ struct BtorDumper
 				++line_num;
 				str = stringf("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type.str()).c_str(), input_a_width+input_b_width, 
 					input_a_line, input_b_line);	
-				fprintf(f, "%s\n", str.c_str());				
+				f << stringf("%s\n", str.c_str());				
 				line_ref[cell->name]=line_num;				
 			}
 			curr_cell.clear();
@@ -825,12 +825,12 @@ struct BtorDumper
 		int l = dump_wire(wire);
 		++line_num;
 		str = stringf("%d root 1 %d", line_num, l);
-		fprintf(f, "%s\n", str.c_str());
+		f << stringf("%s\n", str.c_str());
 	}
 
 	void dump()
 	{
-		fprintf(f, ";module %s\n", cstr(module->name));
+		f << stringf(";module %s\n", cstr(module->name));
 		
 		log("creating intermediate wires map\n");
 		//creating map of intermediate wires as output of some cell
@@ -893,12 +893,12 @@ struct BtorDumper
 			}
 		}
 
-		fprintf(f, ";inputs\n");
+		f << stringf(";inputs\n");
 		for (auto &it : inputs) {
 			RTLIL::Wire *wire = it.second;
 			dump_wire(wire);
 		}
-		fprintf(f, "\n");
+		f << stringf("\n");
 		
 		log("writing memories\n");
 		for(auto mem_it = module->memories.begin(); mem_it != module->memories.end(); ++mem_it)
@@ -921,19 +921,19 @@ struct BtorDumper
 		for(auto it: safety)
 			dump_property(it);
 
-		fprintf(f, "\n");
+		f << stringf("\n");
 		
 		log("writing outputs info\n");
-		fprintf(f, ";outputs\n");
+		f << stringf(";outputs\n");
 		for (auto &it : outputs) {
 			RTLIL::Wire *wire = it.second;
 			int l = dump_wire(wire);
-			fprintf(f, ";%d %s", l, cstr(wire->name));
+			f << stringf(";%d %s", l, cstr(wire->name));
 		}
-		fprintf(f, "\n");
+		f << stringf("\n");
 	}
 
-	static void dump(FILE *f, RTLIL::Module *module, RTLIL::Design *design, BtorDumperConfig &config)
+	static void dump(std::ostream &f, RTLIL::Module *module, RTLIL::Design *design, BtorDumperConfig &config)
 	{
 		BtorDumper dumper(f, module, design, &config);
 		dumper.dump();
@@ -952,7 +952,7 @@ struct BtorBackend : public Backend {
 		log("Write the current design to an BTOR file.\n");
 	}
 
-	virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
+	virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
 	{
 		std::string top_module_name;
 		std::string buf_type, buf_in, buf_out;
@@ -970,10 +970,10 @@ struct BtorBackend : public Backend {
 				if (mod_it.second->get_bool_attribute("\\top"))
 					top_module_name = mod_it.first.str();
 
-		fprintf(f, "; Generated by %s\n", yosys_version_str);
-		fprintf(f, ";  %s developed and maintained by Clifford Wolf <clifford@clifford.at>\n", yosys_version_str);
-		fprintf(f, "; BTOR Backend developed by Ahmed Irfan <irfan@fbk.eu> - Fondazione Bruno Kessler, Trento, Italy\n");
-		fprintf(f, ";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n");
+		*f << stringf("; Generated by %s\n", yosys_version_str);
+		*f << stringf(";  %s developed and maintained by Clifford Wolf <clifford@clifford.at>\n", yosys_version_str);
+		*f << stringf("; BTOR Backend developed by Ahmed Irfan <irfan@fbk.eu> - Fondazione Bruno Kessler, Trento, Italy\n");
+		*f << stringf(";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n");
 		
 		std::vector<RTLIL::Module*> mod_list;
 
@@ -987,7 +987,7 @@ struct BtorBackend : public Backend {
 				log_error("Found unmapped processes in module %s: unmapped processes are not supported in BTOR backend!\n", RTLIL::id2cstr(module->name));
 
 			if (module->name == RTLIL::escape_id(top_module_name)) {
-				BtorDumper::dump(f, module, design, config);
+				BtorDumper::dump(*f, module, design, config);
 				top_module_name.clear();
 				continue;
 			}
@@ -999,7 +999,7 @@ struct BtorBackend : public Backend {
 			log_error("Can't find top module `%s'!\n", top_module_name.c_str());
 
 		for (auto module : mod_list)
-			BtorDumper::dump(f, module, design, config);
+			BtorDumper::dump(*f, module, design, config);
 	}
 } BtorBackend;
 
-- 
cgit v1.2.3


From e07698818dfe3c8e5f87b13090c7e70d22189e2a Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 1 Sep 2014 11:36:02 +0200
Subject: Using std::vector<RTLIL::State> instead of RTLIL::Const for
 RTLIL::SigChunk::data

---
 backends/btor/btor.cc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'backends/btor/btor.cc')

diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index 9b770518..3482faa7 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -294,7 +294,8 @@ struct BtorDumper
 		int l=-1;
 		if(chunk->wire == NULL)
 		{
-			l=dump_const(&chunk->data, chunk->width, chunk->offset);			
+			RTLIL::Const data_const(chunk->data);
+			l=dump_const(&data_const, chunk->width, chunk->offset);			
 		}
 		else
 		{
-- 
cgit v1.2.3