From f9946232adf887e5aa4a48c64f88eaa17e424009 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 01:49:51 +0200 Subject: Refactoring: Renamed RTLIL::Module::wires to wires_ --- backends/btor/btor.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'backends/btor/btor.cc') diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc index f731e17e..f1e95ee1 100644 --- a/backends/btor/btor.cc +++ b/backends/btor/btor.cc @@ -80,7 +80,7 @@ struct BtorDumper { line_num=0; str.clear(); - for(auto it=module->wires.begin(); it!=module->wires.end(); ++it) + for(auto it=module->wires_.begin(); it!=module->wires_.end(); ++it) { if(it->second->port_input) { @@ -880,7 +880,7 @@ struct BtorDumper std::map inputs, outputs; std::vector safety; - for (auto &wire_it : module->wires) { + for (auto &wire_it : module->wires_) { RTLIL::Wire *wire = wire_it.second; if (wire->port_input) inputs[wire->port_id] = wire; -- cgit v1.2.3