From 5dce303a2a2c27d50e99856b6f33467798e13020 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 23 Aug 2014 13:54:21 +0200 Subject: Changed backend-api from FILE to std::ostream --- backends/edif/edif.cc | 138 +++++++++++++++++++++++++------------------------- 1 file changed, 69 insertions(+), 69 deletions(-) (limited to 'backends/edif') diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index ecdfaabf..ccedd91d 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -103,7 +103,7 @@ struct EdifBackend : public Backend { log("is targeted.\n"); log("\n"); } - virtual void execute(FILE *&f, std::string filename, std::vector args, RTLIL::Design *design) + virtual void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) { log_header("Executing EDIF backend.\n"); @@ -160,38 +160,38 @@ struct EdifBackend : public Backend { if (top_module_name.empty()) log_error("No module found in design!\n"); - fprintf(f, "(edif %s\n", EDIF_DEF(top_module_name)); - fprintf(f, " (edifVersion 2 0 0)\n"); - fprintf(f, " (edifLevel 0)\n"); - fprintf(f, " (keywordMap (keywordLevel 0))\n"); - fprintf(f, " (comment \"Generated by %s\")\n", yosys_version_str); - - fprintf(f, " (external LIB\n"); - fprintf(f, " (edifLevel 0)\n"); - fprintf(f, " (technology (numberDefinition))\n"); - - fprintf(f, " (cell GND\n"); - fprintf(f, " (cellType GENERIC)\n"); - fprintf(f, " (view VIEW_NETLIST\n"); - fprintf(f, " (viewType NETLIST)\n"); - fprintf(f, " (interface (port G (direction OUTPUT)))\n"); - fprintf(f, " )\n"); - fprintf(f, " )\n"); - - fprintf(f, " (cell VCC\n"); - fprintf(f, " (cellType GENERIC)\n"); - fprintf(f, " (view VIEW_NETLIST\n"); - fprintf(f, " (viewType NETLIST)\n"); - fprintf(f, " (interface (port P (direction OUTPUT)))\n"); - fprintf(f, " )\n"); - fprintf(f, " )\n"); + *f << stringf("(edif %s\n", EDIF_DEF(top_module_name)); + *f << stringf(" (edifVersion 2 0 0)\n"); + *f << stringf(" (edifLevel 0)\n"); + *f << stringf(" (keywordMap (keywordLevel 0))\n"); + *f << stringf(" (comment \"Generated by %s\")\n", yosys_version_str); + + *f << stringf(" (external LIB\n"); + *f << stringf(" (edifLevel 0)\n"); + *f << stringf(" (technology (numberDefinition))\n"); + + *f << stringf(" (cell GND\n"); + *f << stringf(" (cellType GENERIC)\n"); + *f << stringf(" (view VIEW_NETLIST\n"); + *f << stringf(" (viewType NETLIST)\n"); + *f << stringf(" (interface (port G (direction OUTPUT)))\n"); + *f << stringf(" )\n"); + *f << stringf(" )\n"); + + *f << stringf(" (cell VCC\n"); + *f << stringf(" (cellType GENERIC)\n"); + *f << stringf(" (view VIEW_NETLIST\n"); + *f << stringf(" (viewType NETLIST)\n"); + *f << stringf(" (interface (port P (direction OUTPUT)))\n"); + *f << stringf(" )\n"); + *f << stringf(" )\n"); for (auto &cell_it : lib_cell_ports) { - fprintf(f, " (cell %s\n", EDIF_DEF(cell_it.first)); - fprintf(f, " (cellType GENERIC)\n"); - fprintf(f, " (view VIEW_NETLIST\n"); - fprintf(f, " (viewType NETLIST)\n"); - fprintf(f, " (interface\n"); + *f << stringf(" (cell %s\n", EDIF_DEF(cell_it.first)); + *f << stringf(" (cellType GENERIC)\n"); + *f << stringf(" (view VIEW_NETLIST\n"); + *f << stringf(" (viewType NETLIST)\n"); + *f << stringf(" (interface\n"); for (auto &port_it : cell_it.second) { const char *dir = "INOUT"; if (ct.cell_known(cell_it.first)) { @@ -200,13 +200,13 @@ struct EdifBackend : public Backend { else if (!ct.cell_input(cell_it.first, port_it)) dir = "OUTPUT"; } - fprintf(f, " (port %s (direction %s))\n", EDIF_DEF(port_it), dir); + *f << stringf(" (port %s (direction %s))\n", EDIF_DEF(port_it), dir); } - fprintf(f, " )\n"); - fprintf(f, " )\n"); - fprintf(f, " )\n"); + *f << stringf(" )\n"); + *f << stringf(" )\n"); + *f << stringf(" )\n"); } - fprintf(f, " )\n"); + *f << stringf(" )\n"); std::vector sorted_modules; @@ -238,9 +238,9 @@ struct EdifBackend : public Backend { } - fprintf(f, " (library DESIGN\n"); - fprintf(f, " (edifLevel 0)\n"); - fprintf(f, " (technology (numberDefinition))\n"); + *f << stringf(" (library DESIGN\n"); + *f << stringf(" (edifLevel 0)\n"); + *f << stringf(" (technology (numberDefinition))\n"); for (auto module : sorted_modules) { if (module->get_bool_attribute("\\blackbox")) @@ -249,11 +249,11 @@ struct EdifBackend : public Backend { SigMap sigmap(module); std::map> net_join_db; - fprintf(f, " (cell %s\n", EDIF_DEF(module->name)); - fprintf(f, " (cellType GENERIC)\n"); - fprintf(f, " (view VIEW_NETLIST\n"); - fprintf(f, " (viewType NETLIST)\n"); - fprintf(f, " (interface\n"); + *f << stringf(" (cell %s\n", EDIF_DEF(module->name)); + *f << stringf(" (cellType GENERIC)\n"); + *f << stringf(" (view VIEW_NETLIST\n"); + *f << stringf(" (viewType NETLIST)\n"); + *f << stringf(" (interface\n"); for (auto &wire_it : module->wires_) { RTLIL::Wire *wire = wire_it.second; if (wire->port_id == 0) @@ -264,31 +264,31 @@ struct EdifBackend : public Backend { else if (!wire->port_input) dir = "OUTPUT"; if (wire->width == 1) { - fprintf(f, " (port %s (direction %s))\n", EDIF_DEF(wire->name), dir); + *f << stringf(" (port %s (direction %s))\n", EDIF_DEF(wire->name), dir); RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire)); net_join_db[sig].insert(stringf("(portRef %s)", EDIF_REF(wire->name))); } else { - fprintf(f, " (port (array %s %d) (direction %s))\n", EDIF_DEF(wire->name), wire->width, dir); + *f << stringf(" (port (array %s %d) (direction %s))\n", EDIF_DEF(wire->name), wire->width, dir); for (int i = 0; i < wire->width; i++) { RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire, i)); net_join_db[sig].insert(stringf("(portRef (member %s %d))", EDIF_REF(wire->name), i)); } } } - fprintf(f, " )\n"); - fprintf(f, " (contents\n"); - fprintf(f, " (instance GND (viewRef VIEW_NETLIST (cellRef GND (libraryRef LIB))))\n"); - fprintf(f, " (instance VCC (viewRef VIEW_NETLIST (cellRef VCC (libraryRef LIB))))\n"); + *f << stringf(" )\n"); + *f << stringf(" (contents\n"); + *f << stringf(" (instance GND (viewRef VIEW_NETLIST (cellRef GND (libraryRef LIB))))\n"); + *f << stringf(" (instance VCC (viewRef VIEW_NETLIST (cellRef VCC (libraryRef LIB))))\n"); for (auto &cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; - fprintf(f, " (instance %s\n", EDIF_DEF(cell->name)); - fprintf(f, " (viewRef VIEW_NETLIST (cellRef %s%s))", EDIF_REF(cell->type), + *f << stringf(" (instance %s\n", EDIF_DEF(cell->name)); + *f << stringf(" (viewRef VIEW_NETLIST (cellRef %s%s))", EDIF_REF(cell->type), lib_cell_ports.count(cell->type) > 0 ? " (libraryRef LIB)" : ""); for (auto &p : cell->parameters) if ((p.second.flags & RTLIL::CONST_FLAG_STRING) != 0) - fprintf(f, "\n (property %s (string \"%s\"))", EDIF_DEF(p.first), p.second.decode_string().c_str()); + *f << stringf("\n (property %s (string \"%s\"))", EDIF_DEF(p.first), p.second.decode_string().c_str()); else if (p.second.bits.size() <= 32 && RTLIL::SigSpec(p.second).is_fully_def()) - fprintf(f, "\n (property %s (integer %u))", EDIF_DEF(p.first), p.second.as_int()); + *f << stringf("\n (property %s (integer %u))", EDIF_DEF(p.first), p.second.as_int()); else { std::string hex_string = ""; for (size_t i = 0; i < p.second.bits.size(); i += 4) { @@ -300,9 +300,9 @@ struct EdifBackend : public Backend { char digit_str[2] = { "0123456789abcdef"[digit_value], 0 }; hex_string = std::string(digit_str) + hex_string; } - fprintf(f, "\n (property %s (string \"%s\"))", EDIF_DEF(p.first), hex_string.c_str()); + *f << stringf("\n (property %s (string \"%s\"))", EDIF_DEF(p.first), hex_string.c_str()); } - fprintf(f, ")\n"); + *f << stringf(")\n"); for (auto &p : cell->connections()) { RTLIL::SigSpec sig = sigmap(p.second); for (int i = 0; i < SIZE(sig); i++) @@ -320,28 +320,28 @@ struct EdifBackend : public Backend { for (size_t i = 0; i < netname.size(); i++) if (netname[i] == ' ' || netname[i] == '\\') netname.erase(netname.begin() + i--); - fprintf(f, " (net %s (joined\n", EDIF_DEF(netname)); + *f << stringf(" (net %s (joined\n", EDIF_DEF(netname)); for (auto &ref : it.second) - fprintf(f, " %s\n", ref.c_str()); + *f << stringf(" %s\n", ref.c_str()); if (sig.wire == NULL) { if (sig == RTLIL::State::S0) - fprintf(f, " (portRef G (instanceRef GND))\n"); + *f << stringf(" (portRef G (instanceRef GND))\n"); if (sig == RTLIL::State::S1) - fprintf(f, " (portRef P (instanceRef VCC))\n"); + *f << stringf(" (portRef P (instanceRef VCC))\n"); } - fprintf(f, " ))\n"); + *f << stringf(" ))\n"); } - fprintf(f, " )\n"); - fprintf(f, " )\n"); - fprintf(f, " )\n"); + *f << stringf(" )\n"); + *f << stringf(" )\n"); + *f << stringf(" )\n"); } - fprintf(f, " )\n"); + *f << stringf(" )\n"); - fprintf(f, " (design %s\n", EDIF_DEF(top_module_name)); - fprintf(f, " (cellRef %s (libraryRef DESIGN))\n", EDIF_REF(top_module_name)); - fprintf(f, " )\n"); + *f << stringf(" (design %s\n", EDIF_DEF(top_module_name)); + *f << stringf(" (cellRef %s (libraryRef DESIGN))\n", EDIF_REF(top_module_name)); + *f << stringf(" )\n"); - fprintf(f, ")\n"); + *f << stringf(")\n"); } } EdifBackend; -- cgit v1.2.3