From 10e5791c5e5660cb784503d36439ee90d61eb06b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 10:18:00 +0200 Subject: Refactoring: Renamed RTLIL::Design::modules to modules_ --- backends/intersynth/intersynth.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'backends/intersynth/intersynth.cc') diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index a463f5ec..2f94e290 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -121,7 +121,7 @@ struct IntersynthBackend : public Backend { for (auto lib : libs) ct.setup_design(lib); - for (auto module_it : design->modules) + for (auto module_it : design->modules_) { RTLIL::Module *module = module_it.second; SigMap sigmap(module); -- cgit v1.2.3