From 4c4b6021562c598c4510831bd547edaa97d14dac Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 27 Jul 2014 01:51:45 +0200
Subject: Refactoring: Renamed RTLIL::Module::cells to cells_

---
 backends/intersynth/intersynth.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'backends/intersynth/intersynth.cc')

diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc
index 4e8c321b..a463f5ec 100644
--- a/backends/intersynth/intersynth.cc
+++ b/backends/intersynth/intersynth.cc
@@ -128,7 +128,7 @@ struct IntersynthBackend : public Backend {
 
 			if (module->get_bool_attribute("\\blackbox"))
 				continue;
-			if (module->memories.size() == 0 && module->processes.size() == 0 && module->cells.size() == 0)
+			if (module->memories.size() == 0 && module->processes.size() == 0 && module->cells_.size() == 0)
 				continue;
 
 			if (selected && !design->selected_whole_module(module->name)) {
@@ -159,7 +159,7 @@ struct IntersynthBackend : public Backend {
 			}
 
 			// Submodules: "std::set<string> celltypes_code" prevents duplicate cell types 
-			for (auto cell_it : module->cells)
+			for (auto cell_it : module->cells_)
 			{
 				RTLIL::Cell *cell = cell_it.second;
 				std::string celltype_code, node_code;
-- 
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