From 295e352ba6aa1bd71431abc21a8f93735968cae6 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 22 Nov 2013 15:01:12 +0100
Subject: Renamed "placeholder" to "blackbox"

---
 backends/blif/blif.cc               |  2 +-
 backends/edif/edif.cc               |  6 +++---
 backends/intersynth/intersynth.cc   |  2 +-
 backends/spice/spice.cc             |  4 ++--
 backends/verilog/verilog_backend.cc | 14 +++++++-------
 5 files changed, 14 insertions(+), 14 deletions(-)

(limited to 'backends')

diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc
index 9379fce5..27f08774 100644
--- a/backends/blif/blif.cc
+++ b/backends/blif/blif.cc
@@ -300,7 +300,7 @@ struct BlifBackend : public Backend {
 		for (auto module_it : design->modules)
 		{
 			RTLIL::Module *module = module_it.second;
-			if (module->get_bool_attribute("\\placeholder"))
+			if (module->get_bool_attribute("\\blackbox"))
 				continue;
 
 			if (module->processes.size() != 0)
diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc
index 17ae08cc..c5977bb1 100644
--- a/backends/edif/edif.cc
+++ b/backends/edif/edif.cc
@@ -121,7 +121,7 @@ struct EdifBackend : public Backend {
 		for (auto module_it : design->modules)
 		{
 			RTLIL::Module *module = module_it.second;
-			if (module->get_bool_attribute("\\placeholder"))
+			if (module->get_bool_attribute("\\blackbox"))
 				continue;
 
 			if (top_module_name.empty())
@@ -135,7 +135,7 @@ struct EdifBackend : public Backend {
 			for (auto cell_it : module->cells)
 			{
 				RTLIL::Cell *cell = cell_it.second;
-				if (!design->modules.count(cell->type) || design->modules.at(cell->type)->get_bool_attribute("\\placeholder")) {
+				if (!design->modules.count(cell->type) || design->modules.at(cell->type)->get_bool_attribute("\\blackbox")) {
 					lib_cell_ports[cell->type];
 					for (auto p : cell->connections) {
 						if (p.second.width > 1)
@@ -233,7 +233,7 @@ struct EdifBackend : public Backend {
 		fprintf(f, "    (technology (numberDefinition))\n");
 		for (auto module : sorted_modules)
 		{
-			if (module->get_bool_attribute("\\placeholder"))
+			if (module->get_bool_attribute("\\blackbox"))
 				continue;
 
 			SigMap sigmap(module);
diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc
index a3f61eeb..402c3e7c 100644
--- a/backends/intersynth/intersynth.cc
+++ b/backends/intersynth/intersynth.cc
@@ -132,7 +132,7 @@ struct IntersynthBackend : public Backend {
 			RTLIL::Module *module = module_it.second;
 			SigMap sigmap(module);
 
-			if (module->get_bool_attribute("\\placeholder"))
+			if (module->get_bool_attribute("\\blackbox"))
 				continue;
 			if (module->memories.size() == 0 && module->processes.size() == 0 && module->cells.size() == 0)
 				continue;
diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc
index e1a196b8..6c8a3ec9 100644
--- a/backends/spice/spice.cc
+++ b/backends/spice/spice.cc
@@ -57,7 +57,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de
 
 		if (design->modules.count(cell->type) == 0)
 		{
-			log("Warning: no (placeholder) module for cell type `%s' (%s.%s) found! Guessing order of ports.\n",
+			log("Warning: no (blackbox) module for cell type `%s' (%s.%s) found! Guessing order of ports.\n",
 					RTLIL::id2cstr(cell->type), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name));
 			for (auto &conn : cell->connections) {
 				RTLIL::SigSpec sig = sigmap(conn.second);
@@ -178,7 +178,7 @@ struct SpiceBackend : public Backend {
 		for (auto module_it : design->modules)
 		{
 			RTLIL::Module *module = module_it.second;
-			if (module->get_bool_attribute("\\placeholder"))
+			if (module->get_bool_attribute("\\blackbox"))
 				continue;
 
 			if (module->processes.size() != 0)
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index b9d5e5ec..d733bdc5 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -941,9 +941,9 @@ struct VerilogBackend : public Backend {
 		log("        without this option all internal cells are converted to verilog\n");
 		log("        expressions.\n");
 		log("\n");
-		log("    -placeholders\n");
-		log("        usually modules with the 'placeholder' attribute are ignored. with\n");
-		log("        this option set only the modules with the 'placeholder' attribute\n");
+		log("    -blackboxes\n");
+		log("        usually modules with the 'blackbox' attribute are ignored. with\n");
+		log("        this option set only the modules with the 'blackbox' attribute\n");
 		log("        are written to the output file.\n");
 		log("\n");
 		log("    -selected\n");
@@ -960,7 +960,7 @@ struct VerilogBackend : public Backend {
 		attr2comment = false;
 		noexpr = false;
 
-		bool placeholders = false;
+		bool blackboxes = false;
 		bool selected = false;
 
 		reg_ct.clear();
@@ -988,8 +988,8 @@ struct VerilogBackend : public Backend {
 				noexpr = true;
 				continue;
 			}
-			if (arg == "-placeholders") {
-				placeholders = true;
+			if (arg == "-blackboxes") {
+				blackboxes = true;
 				continue;
 			}
 			if (arg == "-selected") {
@@ -1002,7 +1002,7 @@ struct VerilogBackend : public Backend {
 
 		fprintf(f, "/* Generated by %s */\n", yosys_version_str);
 		for (auto it = design->modules.begin(); it != design->modules.end(); it++) {
-			if (it->second->get_bool_attribute("\\placeholder") != placeholders)
+			if (it->second->get_bool_attribute("\\blackbox") != blackboxes)
 				continue;
 			if (selected && !design->selected_whole_module(it->first)) {
 				if (design->selected_module(it->first))
-- 
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