From 4b4048bc5feba1ab05c7a63f12c0a17879cb7e04 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 22 Jul 2014 20:15:14 +0200 Subject: SigSpec refactoring: using the accessor functions everywhere --- backends/autotest/autotest.cc | 4 +- backends/blif/blif.cc | 24 +++++------ backends/btor/btor.cc | 80 ++++++++++++++++++------------------- backends/edif/edif.cc | 20 +++++----- backends/ilang/ilang_backend.cc | 8 ++-- backends/intersynth/intersynth.cc | 24 +++++------ backends/spice/spice.cc | 22 +++++----- backends/verilog/verilog_backend.cc | 58 +++++++++++++-------------- 8 files changed, 120 insertions(+), 120 deletions(-) (limited to 'backends') diff --git a/backends/autotest/autotest.cc b/backends/autotest/autotest.cc index e7fbfe7a..028d1f37 100644 --- a/backends/autotest/autotest.cc +++ b/backends/autotest/autotest.cc @@ -119,8 +119,8 @@ static void autotest(FILE *f, RTLIL::Design *design) if ((*it4)->type == RTLIL::ST0 || (*it4)->type == RTLIL::ST1) continue; RTLIL::SigSpec &signal = (*it4)->signal; - for (size_t i = 0; i < signal.__chunks.size(); i++) { - if (signal.__chunks[i].wire == wire) + for (size_t i = 0; i < signal.chunks().size(); i++) { + if (signal.chunks()[i].wire == wire) is_clksignal = true; } } diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc index 2d446610..90d1b3fc 100644 --- a/backends/blif/blif.cc +++ b/backends/blif/blif.cc @@ -71,18 +71,18 @@ struct BlifDumper const char *cstr(RTLIL::SigSpec sig) { sig.optimize(); - log_assert(sig.__width == 1); + log_assert(sig.size() == 1); - if (sig.__chunks.at(0).wire == NULL) - return sig.__chunks.at(0).data.bits.at(0) == RTLIL::State::S1 ? "$true" : "$false"; + if (sig.chunks().at(0).wire == NULL) + return sig.chunks().at(0).data.bits.at(0) == RTLIL::State::S1 ? "$true" : "$false"; - std::string str = RTLIL::unescape_id(sig.__chunks.at(0).wire->name); + std::string str = RTLIL::unescape_id(sig.chunks().at(0).wire->name); for (size_t i = 0; i < str.size(); i++) if (str[i] == '#' || str[i] == '=') str[i] = '?'; - if (sig.__chunks.at(0).wire->width != 1) - str += stringf("[%d]", sig.__chunks.at(0).offset); + if (sig.chunks().at(0).wire->width != 1) + str += stringf("[%d]", sig.chunks().at(0).offset); cstr_buf.push_back(str); return cstr_buf.back().c_str(); @@ -194,12 +194,12 @@ struct BlifDumper fprintf(f, ".names"); auto &inputs = cell->connections.at("\\I"); auto width = cell->parameters.at("\\WIDTH").as_int(); - log_assert(inputs.__width == width); - for (int i = 0; i < inputs.__width; i++) { + log_assert(inputs.size() == width); + for (int i = 0; i < inputs.size(); i++) { fprintf(f, " %s", cstr(inputs.extract(i, 1))); } auto &output = cell->connections.at("\\O"); - log_assert(output.__width == 1); + log_assert(output.size() == 1); fprintf(f, " %s", cstr(output)); fprintf(f, "\n"); auto mask = cell->parameters.at("\\LUT").as_string(); @@ -215,8 +215,8 @@ struct BlifDumper fprintf(f, ".%s %s", subckt_or_gate(cell->type), cstr(cell->type)); for (auto &conn : cell->connections) - for (int i = 0; i < conn.second.__width; i++) { - if (conn.second.__width == 1) + for (int i = 0; i < conn.second.size(); i++) { + if (conn.second.size() == 1) fprintf(f, " %s", cstr(conn.first)); else fprintf(f, " %s[%d]", cstr(conn.first), i); @@ -244,7 +244,7 @@ struct BlifDumper } for (auto &conn : module->connections) - for (int i = 0; i < conn.first.__width; i++) + for (int i = 0; i < conn.first.size(); i++) if (config->conn_mode) fprintf(f, ".conn %s %s\n", cstr(conn.second.extract(i, 1)), cstr(conn.first.extract(i, 1))); else if (!config->buf_type.empty()) diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc index 428e9a88..7853160e 100644 --- a/backends/btor/btor.cc +++ b/backends/btor/btor.cc @@ -196,7 +196,7 @@ struct BtorDumper RTLIL::SigSpec* cell_output = get_cell_output(cell); int cell_line = dump_cell(cell); - if(dep_set.size()==1 && wire->width == cell_output->__width) + if(dep_set.size()==1 && wire->width == cell_output->size()) { wire_line = cell_line; break; @@ -205,17 +205,17 @@ struct BtorDumper { int prev_wire_line=0; //previously dumped wire line int start_bit=0; - for(unsigned j=0; j__chunks.size(); ++j) + for(unsigned j=0; jchunks().size(); ++j) { - start_bit+=cell_output->__chunks[j].width; - if(cell_output->__chunks[j].wire->name == wire->name) + start_bit+=cell_output->chunks()[j].width; + if(cell_output->chunks()[j].wire->name == wire->name) { prev_wire_line = wire_line; wire_line = ++line_num; - str = stringf("%d slice %d %d %d %d;1", line_num, cell_output->__chunks[j].width, - cell_line, start_bit-1, start_bit-cell_output->__chunks[j].width); + str = stringf("%d slice %d %d %d %d;1", line_num, cell_output->chunks()[j].width, + cell_line, start_bit-1, start_bit-cell_output->chunks()[j].width); fprintf(f, "%s\n", str.c_str()); - wire_width += cell_output->__chunks[j].width; + wire_width += cell_output->chunks()[j].width; if(prev_wire_line!=0) { ++line_num; @@ -231,7 +231,7 @@ struct BtorDumper { log(" - checking sigmap\n"); RTLIL::SigSpec s = RTLIL::SigSpec(wire); - wire_line = dump_sigspec(&s, s.__width); + wire_line = dump_sigspec(&s, s.size()); line_ref[wire->name]=wire_line; } line_ref[wire->name]=wire_line; @@ -320,21 +320,21 @@ struct BtorDumper auto it = sig_ref.find(s); if(it == std::end(sig_ref)) { - if (s.__chunks.size() == 1) + if (s.chunks().size() == 1) { - l = dump_sigchunk(&s.__chunks[0]); + l = dump_sigchunk(&s.chunks()[0]); } else { int l1, l2, w1, w2; - l1 = dump_sigchunk(&s.__chunks[0]); + l1 = dump_sigchunk(&s.chunks()[0]); log_assert(l1>0); - w1 = s.__chunks[0].width; - for (unsigned i=1; i < s.__chunks.size(); ++i) + w1 = s.chunks()[0].width; + for (unsigned i=1; i < s.chunks().size(); ++i) { - l2 = dump_sigchunk(&s.__chunks[i]); + l2 = dump_sigchunk(&s.chunks()[i]); log_assert(l2>0); - w2 = s.__chunks[i].width; + w2 = s.chunks()[i].width; ++line_num; str = stringf("%d concat %d %d %d", line_num, w1+w2, l2, l1); fprintf(f, "%s\n", str.c_str()); @@ -350,22 +350,22 @@ struct BtorDumper l = it->second; } - if (expected_width != s.__width) + if (expected_width != s.size()) { log(" - changing width of sigspec\n"); //TODO: this block may not be needed anymore, due to explicit type conversion by "splice" command - if(expected_width > s.__width) + if(expected_width > s.size()) { //TODO: case the signal is signed ++line_num; - str = stringf ("%d zero %d", line_num, expected_width - s.__width); + str = stringf ("%d zero %d", line_num, expected_width - s.size()); fprintf(f, "%s\n", str.c_str()); ++line_num; str = stringf ("%d concat %d %d %d", line_num, expected_width, line_num-1, l); fprintf(f, "%s\n", str.c_str()); l = line_num; } - else if(expected_width < s.__width) + else if(expected_width < s.size()) { ++line_num; str = stringf ("%d slice %d %d %d %d;3", line_num, expected_width, l, expected_width-1, 0); @@ -389,8 +389,8 @@ struct BtorDumper log("writing assert cell - %s\n", cstr(cell->type)); const RTLIL::SigSpec* expr = &cell->connections.at(RTLIL::IdString("\\A")); const RTLIL::SigSpec* en = &cell->connections.at(RTLIL::IdString("\\EN")); - log_assert(expr->__width == 1); - log_assert(en->__width == 1); + log_assert(expr->size() == 1); + log_assert(en->size() == 1); int expr_line = dump_sigspec(expr, 1); int en_line = dump_sigspec(en, 1); int one_line = ++line_num; @@ -649,13 +649,13 @@ struct BtorDumper const RTLIL::SigSpec* cell_output = &cell->connections.at(RTLIL::IdString("\\Q")); int value = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\D")), output_width); unsigned start_bit = 0; - for(unsigned i=0; i__chunks.size(); ++i) + for(unsigned i=0; ichunks().size(); ++i) { - output_width = cell_output->__chunks[i].width; - log_assert( output_width == cell_output->__chunks[i].wire->width);//full reg is given the next value - int reg = dump_wire(cell_output->__chunks[i].wire);//register + output_width = cell_output->chunks()[i].width; + log_assert( output_width == cell_output->chunks()[i].wire->width);//full reg is given the next value + int reg = dump_wire(cell_output->chunks()[i].wire);//register int slice = value; - if(cell_output->__chunks.size()>1) + if(cell_output->chunks().size()>1) { start_bit+=output_width; slice = ++line_num; @@ -759,11 +759,11 @@ struct BtorDumper log("writing slice cell\n"); const RTLIL::SigSpec* input = &cell->connections.at(RTLIL::IdString("\\A")); int input_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int(); - log_assert(input->__width == input_width); + log_assert(input->size() == input_width); int input_line = dump_sigspec(input, input_width); const RTLIL::SigSpec* output = &cell->connections.at(RTLIL::IdString("\\Y")); int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int(); - log_assert(output->__width == output_width); + log_assert(output->size() == output_width); int offset = cell->parameters.at(RTLIL::IdString("\\OFFSET")).as_int(); ++line_num; str = stringf("%d %s %d %d %d %d", line_num, cell_type_translation.at(cell->type).c_str(), output_width, input_line, output_width+offset-1, offset); @@ -775,11 +775,11 @@ struct BtorDumper log("writing concat cell\n"); const RTLIL::SigSpec* input_a = &cell->connections.at(RTLIL::IdString("\\A")); int input_a_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int(); - log_assert(input_a->__width == input_a_width); + log_assert(input_a->size() == input_a_width); int input_a_line = dump_sigspec(input_a, input_a_width); const RTLIL::SigSpec* input_b = &cell->connections.at(RTLIL::IdString("\\B")); int input_b_width = cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int(); - log_assert(input_b->__width == input_b_width); + log_assert(input_b->size() == input_b_width); int input_b_line = dump_sigspec(input_b, input_b_width); ++line_num; str = stringf("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type).c_str(), input_a_width+input_b_width, @@ -843,11 +843,11 @@ struct BtorDumper log(" - %s\n", cstr(it->second->type)); if (cell->type == "$memrd") { - for(unsigned i=0; i__chunks.size(); ++i) + for(unsigned i=0; ichunks().size(); ++i) { - RTLIL::Wire *w = output_sig->__chunks[i].wire; + RTLIL::Wire *w = output_sig->chunks()[i].wire; RTLIL::IdString wire_id = w->name; - inter_wire_map[wire_id].insert(WireInfo(cell->name,&output_sig->__chunks[i])); + inter_wire_map[wire_id].insert(WireInfo(cell->name,&output_sig->chunks()[i])); } } else if(cell->type == "$memwr") @@ -856,22 +856,22 @@ struct BtorDumper } else if(cell->type == "$dff" || cell->type == "$adff" || cell->type == "$dffsr") { - RTLIL::IdString wire_id = output_sig->__chunks[0].wire->name; - for(unsigned i=0; i__chunks.size(); ++i) + RTLIL::IdString wire_id = output_sig->chunks()[0].wire->name; + for(unsigned i=0; ichunks().size(); ++i) { - RTLIL::Wire *w = output_sig->__chunks[i].wire; + RTLIL::Wire *w = output_sig->chunks()[i].wire; RTLIL::IdString wire_id = w->name; - inter_wire_map[wire_id].insert(WireInfo(cell->name,&output_sig->__chunks[i])); + inter_wire_map[wire_id].insert(WireInfo(cell->name,&output_sig->chunks()[i])); basic_wires[wire_id] = true; } } else { - for(unsigned i=0; i__chunks.size(); ++i) + for(unsigned i=0; ichunks().size(); ++i) { - RTLIL::Wire *w = output_sig->__chunks[i].wire; + RTLIL::Wire *w = output_sig->chunks()[i].wire; RTLIL::IdString wire_id = w->name; - inter_wire_map[wire_id].insert(WireInfo(cell->name,&output_sig->__chunks[i])); + inter_wire_map[wire_id].insert(WireInfo(cell->name,&output_sig->chunks()[i])); } } } diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index c239ef30..bb2b26e2 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -149,7 +149,7 @@ struct EdifBackend : public Backend { if (!design->modules.count(cell->type) || design->modules.at(cell->type)->get_bool_attribute("\\blackbox")) { lib_cell_ports[cell->type]; for (auto p : cell->connections) { - if (p.second.__width > 1) + if (p.second.size() > 1) log_error("Found multi-bit port %s on library cell %s.%s (%s): not supported in EDIF backend!\n", RTLIL::id2cstr(p.first), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); lib_cell_ports[cell->type].insert(p.first); @@ -307,9 +307,9 @@ struct EdifBackend : public Backend { for (auto &p : cell->connections) { RTLIL::SigSpec sig = sigmap(p.second); sig.expand(); - for (int i = 0; i < sig.__width; i++) { - RTLIL::SigSpec sigbit(sig.__chunks.at(i)); - if (sig.__width == 1) + for (int i = 0; i < sig.size(); i++) { + RTLIL::SigSpec sigbit(sig.chunks().at(i)); + if (sig.size() == 1) net_join_db[sigbit].insert(stringf("(portRef %s (instanceRef %s))", EDIF_REF(p.first), EDIF_REF(cell->name))); else net_join_db[sigbit].insert(stringf("(portRef (member %s %d) (instanceRef %s))", EDIF_REF(p.first), i, EDIF_REF(cell->name))); @@ -319,9 +319,9 @@ struct EdifBackend : public Backend { for (auto &it : net_join_db) { RTLIL::SigSpec sig = it.first; sig.optimize(); - log_assert(sig.__width == 1); - if (sig.__chunks.at(0).wire == NULL) { - if (sig.__chunks.at(0).data.bits.at(0) != RTLIL::State::S0 && sig.__chunks.at(0).data.bits.at(0) != RTLIL::State::S1) + log_assert(sig.size() == 1); + if (sig.chunks().at(0).wire == NULL) { + if (sig.chunks().at(0).data.bits.at(0) != RTLIL::State::S0 && sig.chunks().at(0).data.bits.at(0) != RTLIL::State::S1) continue; } std::string netname = log_signal(sig); @@ -331,10 +331,10 @@ struct EdifBackend : public Backend { fprintf(f, " (net %s (joined\n", EDIF_DEF(netname)); for (auto &ref : it.second) fprintf(f, " %s\n", ref.c_str()); - if (sig.__chunks.at(0).wire == NULL) { - if (sig.__chunks.at(0).data.bits.at(0) == RTLIL::State::S0) + if (sig.chunks().at(0).wire == NULL) { + if (sig.chunks().at(0).data.bits.at(0) == RTLIL::State::S0) fprintf(f, " (portRef G (instanceRef GND))\n"); - if (sig.__chunks.at(0).data.bits.at(0) == RTLIL::State::S1) + if (sig.chunks().at(0).data.bits.at(0) == RTLIL::State::S1) fprintf(f, " (portRef P (instanceRef VCC))\n"); } fprintf(f, " ))\n"); diff --git a/backends/ilang/ilang_backend.cc b/backends/ilang/ilang_backend.cc index e1a8bfd4..a312b02c 100644 --- a/backends/ilang/ilang_backend.cc +++ b/backends/ilang/ilang_backend.cc @@ -102,11 +102,11 @@ void ILANG_BACKEND::dump_sigchunk(FILE *f, const RTLIL::SigChunk &chunk, bool au void ILANG_BACKEND::dump_sigspec(FILE *f, const RTLIL::SigSpec &sig, bool autoint) { - if (sig.__chunks.size() == 1) { - dump_sigchunk(f, sig.__chunks[0], autoint); + if (sig.chunks().size() == 1) { + dump_sigchunk(f, sig.chunks()[0], autoint); } else { fprintf(f, "{ "); - for (auto it = sig.__chunks.rbegin(); it != sig.__chunks.rend(); it++) { + for (auto it = sig.chunks().rbegin(); it != sig.chunks().rend(); it++) { dump_sigchunk(f, *it, false); fprintf(f, " "); } @@ -314,7 +314,7 @@ void ILANG_BACKEND::dump_module(FILE *f, std::string indent, const RTLIL::Module if (only_selected) { RTLIL::SigSpec sigs = it->first; sigs.append(it->second); - for (auto &c : sigs.__chunks) { + for (auto &c : sigs.chunks()) { if (c.wire == NULL || !design->selected(module, c.wire)) continue; show_conn = true; diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index 049a2ce8..832922de 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -30,23 +30,23 @@ static std::string netname(std::set &conntypes_code, std::setwidth) + if (sig.chunks()[0].offset != 0 || sig.size() != sig.chunks()[0].wire->width) goto error; - return RTLIL::unescape_id(sig.__chunks[0].wire->name); + return RTLIL::unescape_id(sig.chunks()[0].wire->name); } struct IntersynthBackend : public Backend { @@ -177,9 +177,9 @@ struct IntersynthBackend : public Backend { node_code = stringf("node %s %s", RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); for (auto &port : cell->connections) { RTLIL::SigSpec sig = sigmap(port.second); - if (sig.__width != 0) { - conntypes_code.insert(stringf("conntype b%d %d 2 %d\n", sig.__width, sig.__width, sig.__width)); - celltype_code += stringf(" b%d %s%s", sig.__width, ct.cell_output(cell->type, port.first) ? "*" : "", RTLIL::id2cstr(port.first)); + if (sig.size() != 0) { + conntypes_code.insert(stringf("conntype b%d %d 2 %d\n", sig.size(), sig.size(), sig.size())); + celltype_code += stringf(" b%d %s%s", sig.size(), ct.cell_output(cell->type, port.first) ? "*" : "", RTLIL::id2cstr(port.first)); node_code += stringf(" %s %s", RTLIL::id2cstr(port.first), netname(conntypes_code, celltypes_code, constcells_code, sig).c_str()); } } diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc index c7f832c6..8e894caf 100644 --- a/backends/spice/spice.cc +++ b/backends/spice/spice.cc @@ -27,16 +27,16 @@ static void print_spice_net(FILE *f, RTLIL::SigSpec s, std::string &neg, std::string &pos, std::string &ncpf, int &nc_counter) { - log_assert(s.__chunks.size() == 1 && s.__chunks[0].width == 1); - if (s.__chunks[0].wire) { - if (s.__chunks[0].wire->width > 1) - fprintf(f, " %s[%d]", RTLIL::id2cstr(s.__chunks[0].wire->name), s.__chunks[0].offset); + log_assert(s.chunks().size() == 1 && s.chunks()[0].width == 1); + if (s.chunks()[0].wire) { + if (s.chunks()[0].wire->width > 1) + fprintf(f, " %s[%d]", RTLIL::id2cstr(s.chunks()[0].wire->name), s.chunks()[0].offset); else - fprintf(f, " %s", RTLIL::id2cstr(s.__chunks[0].wire->name)); + fprintf(f, " %s", RTLIL::id2cstr(s.chunks()[0].wire->name)); } else { - if (s.__chunks[0].data.bits.at(0) == RTLIL::State::S0) + if (s.chunks()[0].data.bits.at(0) == RTLIL::State::S0) fprintf(f, " %s", neg.c_str()); - else if (s.__chunks[0].data.bits.at(0) == RTLIL::State::S1) + else if (s.chunks()[0].data.bits.at(0) == RTLIL::State::S1) fprintf(f, " %s", pos.c_str()); else fprintf(f, " %s%d", ncpf.c_str(), nc_counter++); @@ -90,9 +90,9 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de } for (auto &sig : port_sigs) { - for (int i = 0; i < sig.__width; i++) { - RTLIL::SigSpec s = sig.extract(big_endian ? sig.__width - 1 - i : i, 1); - log_assert(s.__chunks.size() == 1 && s.__chunks[0].width == 1); + for (int i = 0; i < sig.size(); i++) { + RTLIL::SigSpec s = sig.extract(big_endian ? sig.size() - 1 - i : i, 1); + log_assert(s.chunks().size() == 1 && s.chunks()[0].width == 1); print_spice_net(f, s, neg, pos, ncpf, nc_counter); } } @@ -101,7 +101,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de } for (auto &conn : module->connections) - for (int i = 0; i < conn.first.__width; i++) { + for (int i = 0; i < conn.first.size(); i++) { fprintf(f, "V%d", conn_counter++); print_spice_net(f, conn.first.extract(i, 1), neg, pos, ncpf, nc_counter); print_spice_net(f, conn.second.extract(i, 1), neg, pos, ncpf, nc_counter); diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 6aeb5084..4b60f0fb 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -134,17 +134,17 @@ std::string id(std::string internal_id, bool may_rename = true) bool is_reg_wire(RTLIL::SigSpec sig, std::string ®_name) { sig.optimize(); - if (sig.__chunks.size() != 1 || sig.__chunks[0].wire == NULL) + if (sig.chunks().size() != 1 || sig.chunks()[0].wire == NULL) return false; - if (reg_wires.count(sig.__chunks[0].wire->name) == 0) + if (reg_wires.count(sig.chunks()[0].wire->name) == 0) return false; - reg_name = id(sig.__chunks[0].wire->name); - if (sig.__width != sig.__chunks[0].wire->width) { - if (sig.__width == 1) - reg_name += stringf("[%d]", sig.__chunks[0].wire->start_offset + sig.__chunks[0].offset); + reg_name = id(sig.chunks()[0].wire->name); + if (sig.size() != sig.chunks()[0].wire->width) { + if (sig.size() == 1) + reg_name += stringf("[%d]", sig.chunks()[0].wire->start_offset + sig.chunks()[0].offset); else - reg_name += stringf("[%d:%d]", sig.__chunks[0].wire->start_offset + sig.__chunks[0].offset + sig.__chunks[0].width - 1, - sig.__chunks[0].wire->start_offset + sig.__chunks[0].offset); + reg_name += stringf("[%d:%d]", sig.chunks()[0].wire->start_offset + sig.chunks()[0].offset + sig.chunks()[0].width - 1, + sig.chunks()[0].wire->start_offset + sig.chunks()[0].offset); } return true; } @@ -221,12 +221,12 @@ void dump_sigchunk(FILE *f, RTLIL::SigChunk &chunk, bool no_decimal = false) void dump_sigspec(FILE *f, RTLIL::SigSpec &sig) { - if (sig.__chunks.size() == 1) { - dump_sigchunk(f, sig.__chunks[0]); + if (sig.chunks().size() == 1) { + dump_sigchunk(f, sig.chunks()[0]); } else { fprintf(f, "{ "); - for (auto it = sig.__chunks.rbegin(); it != sig.__chunks.rend(); it++) { - if (it != sig.__chunks.rbegin()) + for (auto it = sig.chunks().rbegin(); it != sig.chunks().rend(); it++) { + if (it != sig.chunks().rbegin()) fprintf(f, ", "); dump_sigchunk(f, *it, true); } @@ -300,11 +300,11 @@ std::string cellname(RTLIL::Cell *cell) if (!norename && cell->name[0] == '$' && reg_ct.cell_known(cell->type) && cell->connections.count("\\Q") > 0) { RTLIL::SigSpec sig = cell->connections["\\Q"]; - if (sig.__width != 1 || sig.is_fully_const()) + if (sig.size() != 1 || sig.is_fully_const()) goto no_special_reg_name; sig.optimize(); - RTLIL::Wire *wire = sig.__chunks[0].wire; + RTLIL::Wire *wire = sig.chunks()[0].wire; if (wire->name[0] != '\\') goto no_special_reg_name; @@ -318,7 +318,7 @@ std::string cellname(RTLIL::Cell *cell) cell_name = cell_name + "_reg"; if (wire->width != 1) - cell_name += stringf("[%d]", wire->start_offset + sig.__chunks[0].offset); + cell_name += stringf("[%d]", wire->start_offset + sig.chunks()[0].offset); if (active_module && active_module->count_id(cell_name) > 0) goto no_special_reg_name; @@ -532,7 +532,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$pmux_safe") { int width = cell->parameters["\\WIDTH"].as_int(); - int s_width = cell->connections["\\S"].__width; + int s_width = cell->connections["\\S"].size(); std::string func_name = cellname(cell); fprintf(f, "%s" "function [%d:0] %s;\n", indent.c_str(), width-1, func_name.c_str()); @@ -725,7 +725,7 @@ void dump_cell(FILE *f, std::string indent, RTLIL::Cell *cell) fprintf(f, ","); first_arg = false; fprintf(f, "\n%s .%s(", indent.c_str(), id(it->first).c_str()); - if (it->second.__width > 0) + if (it->second.size() > 0) dump_sigspec(f, it->second); fprintf(f, ")"); } @@ -751,7 +751,7 @@ void dump_case_body(FILE *f, std::string indent, RTLIL::CaseRule *cs, bool omit_ fprintf(f, "%s" "begin\n", indent.c_str()); for (auto it = cs->actions.begin(); it != cs->actions.end(); it++) { - if (it->first.__width == 0) + if (it->first.size() == 0) continue; fprintf(f, "%s ", indent.c_str()); dump_sigspec(f, it->first); @@ -772,7 +772,7 @@ void dump_case_body(FILE *f, std::string indent, RTLIL::CaseRule *cs, bool omit_ void dump_proc_switch(FILE *f, std::string indent, RTLIL::SwitchRule *sw) { - if (sw->signal.__width == 0) { + if (sw->signal.size() == 0) { fprintf(f, "%s" "begin\n", indent.c_str()); for (auto it = sw->cases.begin(); it != sw->cases.end(); it++) { if ((*it)->compare.size() == 0) @@ -811,9 +811,9 @@ void case_body_find_regs(RTLIL::CaseRule *cs) case_body_find_regs(*it2); for (auto it = cs->actions.begin(); it != cs->actions.end(); it++) { - for (size_t i = 0; i < it->first.__chunks.size(); i++) - if (it->first.__chunks[i].wire) - reg_wires.insert(it->first.__chunks[i].wire->name); + for (size_t i = 0; i < it->first.chunks().size(); i++) + if (it->first.chunks()[i].wire) + reg_wires.insert(it->first.chunks()[i].wire->name); } } @@ -823,9 +823,9 @@ void dump_process(FILE *f, std::string indent, RTLIL::Process *proc, bool find_r case_body_find_regs(&proc->root_case); for (auto it = proc->syncs.begin(); it != proc->syncs.end(); it++) for (auto it2 = (*it)->actions.begin(); it2 != (*it)->actions.end(); it2++) { - for (size_t i = 0; i < it2->first.__chunks.size(); i++) - if (it2->first.__chunks[i].wire) - reg_wires.insert(it2->first.__chunks[i].wire->name); + for (size_t i = 0; i < it2->first.chunks().size(); i++) + if (it2->first.chunks()[i].wire) + reg_wires.insert(it2->first.chunks()[i].wire->name); } return; } @@ -876,7 +876,7 @@ void dump_process(FILE *f, std::string indent, RTLIL::Process *proc, bool find_r } for (auto it = sync->actions.begin(); it != sync->actions.end(); it++) { - if (it->first.__width == 0) + if (it->first.size() == 0) continue; fprintf(f, "%s ", indent.c_str()); dump_sigspec(f, it->first); @@ -911,9 +911,9 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module) RTLIL::SigSpec sig = cell->connections["\\Q"]; sig.optimize(); - if (sig.__chunks.size() == 1 && sig.__chunks[0].wire) - for (int i = 0; i < sig.__chunks[0].width; i++) - reg_bits.insert(std::pair(sig.__chunks[0].wire, sig.__chunks[0].offset+i)); + if (sig.chunks().size() == 1 && sig.chunks()[0].wire) + for (int i = 0; i < sig.chunks()[0].width; i++) + reg_bits.insert(std::pair(sig.chunks()[0].wire, sig.chunks()[0].offset+i)); } for (auto &it : module->wires) { -- cgit v1.2.3