From 84bf862f7c58c2b69babf043ff5032f924a3ee4d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 14 Aug 2015 10:56:05 +0200 Subject: Spell check (by Larry Doolittle) --- backends/btor/btor.cc | 4 ++-- backends/verilog/verilog_backend.cc | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'backends') diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc index 6f02d307..26585f43 100644 --- a/backends/btor/btor.cc +++ b/backends/btor/btor.cc @@ -70,7 +70,7 @@ struct BtorDumper CellTypes ct; SigMap sigmap; - std::map> inter_wire_map;// for maping the intermediate wires that are output of some cell + std::map> inter_wire_map;// for mapping the intermediate wires that are output of some cell std::map line_ref;//mapping of ids to line_num of the btor file std::map sig_ref;//mapping of sigspec to the line_num of the btor file int line_num;//last line number of btor file @@ -722,7 +722,7 @@ struct BtorDumper //registers else if(cell->type == "$dff" || cell->type == "$adff" || cell->type == "$dffsr") { - //TODO: remodelling fo adff cells + //TODO: remodelling of adff cells log("writing cell - %s\n", cstr(cell->type)); int output_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int(); log(" - width is %d\n", output_width); diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 9b806461..e6a86a16 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -284,7 +284,7 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire) f << stringf("[%d:%d] ", wire->width - 1 + wire->start_offset, wire->start_offset); f << stringf("%s;\n", id(wire->name).c_str()); #else - // do not use Verilog-2k "outut reg" syntax in verilog export + // do not use Verilog-2k "output reg" syntax in Verilog export std::string range = ""; if (wire->width != 1) { if (wire->upto) -- cgit v1.2.3