From a6750b375301f2c2ebb51a2496cdf2c820b2546b Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 3 Feb 2014 13:01:45 +0100
Subject: Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)

---
 backends/btor/btor.cc         | 4 ++++
 backends/btor/verilog2btor.sh | 3 ++-
 2 files changed, 6 insertions(+), 1 deletion(-)

(limited to 'backends')

diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index b8ff7bb3..c69d9899 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -716,6 +716,8 @@ struct BtorDumper
 			else if(cell->type == "$memrd")
 			{
 				log("writing memrd cell\n");
+				if (cell->parameters.at("\\CLK_ENABLE").as_bool() == true)
+					log_error("The btor backen does not support $memrd cells with built-in registers. Run memory_dff with -wr_only.\n");
 				str = cell->parameters.at(RTLIL::IdString("\\MEMID")).decode_string();
 				int mem = dump_memory(module->memories.at(RTLIL::IdString(str.c_str())));
 				int address_width = cell->parameters.at(RTLIL::IdString("\\ABITS")).as_int();
@@ -729,6 +731,8 @@ struct BtorDumper
 			else if(cell->type == "$memwr")
 			{
 				log("writing memwr cell\n");
+				if (cell->parameters.at("\\CLK_ENABLE").as_bool() == false)
+					log_error("The btor backen does not support $memwr cells without built-in registers. Run memory_dff (but with -wr_only).\n");
 				int clk = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\CLK")), 1);
 				bool polarity = cell->parameters.at(RTLIL::IdString("\\CLK_POLARITY")).as_bool();
 				int enable = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\EN")), 1);
diff --git a/backends/btor/verilog2btor.sh b/backends/btor/verilog2btor.sh
index a2f9ebc7..06a32c81 100755
--- a/backends/btor/verilog2btor.sh
+++ b/backends/btor/verilog2btor.sh
@@ -25,7 +25,8 @@ proc;
 opt; opt_const -mux_undef; opt;
 rename -hide;;;
 techmap -share_map pmux2mux.v;;
-memory -nomap;;
+memory_dff -wr_only
+memory_collect;;
 flatten;;
 memory_unpack; 
 splitnets -driver;
-- 
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