From b7dda723022ad00c6c0089be888eab319953faa8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 14:32:50 +0200 Subject: Changed users of cell->connections_ to the new API (sed command) git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;' --- backends/blif/blif.cc | 24 +++++------ backends/btor/btor.cc | 68 ++++++++++++++--------------- backends/edif/edif.cc | 4 +- backends/ilang/ilang_backend.cc | 4 +- backends/intersynth/intersynth.cc | 2 +- backends/spice/spice.cc | 8 ++-- backends/verilog/verilog_backend.cc | 86 ++++++++++++++++++------------------- 7 files changed, 98 insertions(+), 98 deletions(-) (limited to 'backends') diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc index 8d80eccd..cb40834b 100644 --- a/backends/blif/blif.cc +++ b/backends/blif/blif.cc @@ -146,56 +146,56 @@ struct BlifDumper if (!config->icells_mode && cell->type == "$_INV_") { fprintf(f, ".names %s %s\n0 1\n", - cstr(cell->connections_.at("\\A")), cstr(cell->connections_.at("\\Y"))); + cstr(cell->get("\\A")), cstr(cell->get("\\Y"))); continue; } if (!config->icells_mode && cell->type == "$_AND_") { fprintf(f, ".names %s %s %s\n11 1\n", - cstr(cell->connections_.at("\\A")), cstr(cell->connections_.at("\\B")), cstr(cell->connections_.at("\\Y"))); + cstr(cell->get("\\A")), cstr(cell->get("\\B")), cstr(cell->get("\\Y"))); continue; } if (!config->icells_mode && cell->type == "$_OR_") { fprintf(f, ".names %s %s %s\n1- 1\n-1 1\n", - cstr(cell->connections_.at("\\A")), cstr(cell->connections_.at("\\B")), cstr(cell->connections_.at("\\Y"))); + cstr(cell->get("\\A")), cstr(cell->get("\\B")), cstr(cell->get("\\Y"))); continue; } if (!config->icells_mode && cell->type == "$_XOR_") { fprintf(f, ".names %s %s %s\n10 1\n01 1\n", - cstr(cell->connections_.at("\\A")), cstr(cell->connections_.at("\\B")), cstr(cell->connections_.at("\\Y"))); + cstr(cell->get("\\A")), cstr(cell->get("\\B")), cstr(cell->get("\\Y"))); continue; } if (!config->icells_mode && cell->type == "$_MUX_") { fprintf(f, ".names %s %s %s %s\n1-0 1\n-11 1\n", - cstr(cell->connections_.at("\\A")), cstr(cell->connections_.at("\\B")), - cstr(cell->connections_.at("\\S")), cstr(cell->connections_.at("\\Y"))); + cstr(cell->get("\\A")), cstr(cell->get("\\B")), + cstr(cell->get("\\S")), cstr(cell->get("\\Y"))); continue; } if (!config->icells_mode && cell->type == "$_DFF_N_") { fprintf(f, ".latch %s %s fe %s\n", - cstr(cell->connections_.at("\\D")), cstr(cell->connections_.at("\\Q")), cstr(cell->connections_.at("\\C"))); + cstr(cell->get("\\D")), cstr(cell->get("\\Q")), cstr(cell->get("\\C"))); continue; } if (!config->icells_mode && cell->type == "$_DFF_P_") { fprintf(f, ".latch %s %s re %s\n", - cstr(cell->connections_.at("\\D")), cstr(cell->connections_.at("\\Q")), cstr(cell->connections_.at("\\C"))); + cstr(cell->get("\\D")), cstr(cell->get("\\Q")), cstr(cell->get("\\C"))); continue; } if (!config->icells_mode && cell->type == "$lut") { fprintf(f, ".names"); - auto &inputs = cell->connections_.at("\\I"); + auto &inputs = cell->get("\\I"); auto width = cell->parameters.at("\\WIDTH").as_int(); log_assert(inputs.size() == width); for (int i = 0; i < inputs.size(); i++) { fprintf(f, " %s", cstr(inputs.extract(i, 1))); } - auto &output = cell->connections_.at("\\O"); + auto &output = cell->get("\\O"); log_assert(output.size() == 1); fprintf(f, " %s", cstr(output)); fprintf(f, "\n"); @@ -211,7 +211,7 @@ struct BlifDumper } fprintf(f, ".%s %s", subckt_or_gate(cell->type), cstr(cell->type)); - for (auto &conn : cell->connections_) + for (auto &conn : cell->connections()) for (int i = 0; i < conn.second.size(); i++) { if (conn.second.size() == 1) fprintf(f, " %s", cstr(conn.first)); @@ -240,7 +240,7 @@ struct BlifDumper } } - for (auto &conn : module->connections_) + for (auto &conn : module->connections()) for (int i = 0; i < conn.first.size(); i++) if (config->conn_mode) fprintf(f, ".conn %s %s\n", cstr(conn.second.extract(i, 1)), cstr(conn.first.extract(i, 1))); diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc index 46edec9c..0316f7ab 100644 --- a/backends/btor/btor.cc +++ b/backends/btor/btor.cc @@ -387,8 +387,8 @@ struct BtorDumper if(cell->type == "$assert") { log("writing assert cell - %s\n", cstr(cell->type)); - const RTLIL::SigSpec* expr = &cell->connections_.at(RTLIL::IdString("\\A")); - const RTLIL::SigSpec* en = &cell->connections_.at(RTLIL::IdString("\\EN")); + const RTLIL::SigSpec* expr = &cell->connections().at(RTLIL::IdString("\\A")); + const RTLIL::SigSpec* en = &cell->connections().at(RTLIL::IdString("\\EN")); log_assert(expr->size() == 1); log_assert(en->size() == 1); int expr_line = dump_sigspec(expr, 1); @@ -420,7 +420,7 @@ struct BtorDumper int w = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int(); int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int(); w = w>output_width ? w:output_width; //padding of w - int l = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\A")), w); + int l = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\A")), w); int cell_line = l; if(cell->type != "$pos") { @@ -444,7 +444,7 @@ struct BtorDumper int w = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int(); int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int(); log_assert(output_width == 1); - int l = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\A")), w); + int l = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\A")), w); if(cell->type == "$logic_not" && w > 1) { ++line_num; @@ -481,8 +481,8 @@ struct BtorDumper l1_width = l1_width > l2_width ? l1_width : l2_width; l2_width = l2_width > l1_width ? l2_width : l1_width; - int l1 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\A")), l1_width); - int l2 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\B")), l2_width); + int l1 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\A")), l1_width); + int l2 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\B")), l2_width); ++line_num; std::string op = cell_type_translation.at(cell->type); @@ -515,8 +515,8 @@ struct BtorDumper l1_width = l1_width > l2_width ? l1_width : l2_width; l2_width = l2_width > l1_width ? l2_width : l1_width; - int l1 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\A")), l1_width); - int l2 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\B")), l2_width); + int l1 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\A")), l1_width); + int l2 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\B")), l2_width); ++line_num; std::string op = cell_type_translation.at(cell->type); @@ -550,8 +550,8 @@ struct BtorDumper l1_width = pow(2, ceil(log(l1_width)/log(2))); int l2_width = cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int(); //assert(l2_width <= ceil(log(l1_width)/log(2)) ); - int l1 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\A")), l1_width); - int l2 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\B")), ceil(log(l1_width)/log(2))); + int l1 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\A")), l1_width); + int l2 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\B")), ceil(log(l1_width)/log(2))); int cell_output = ++line_num; str = stringf ("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type).c_str(), l1_width, l1, l2); fprintf(f, "%s\n", str.c_str()); @@ -559,7 +559,7 @@ struct BtorDumper if(l2_width > ceil(log(l1_width)/log(2))) { int extra_width = l2_width - ceil(log(l1_width)/log(2)); - l2 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\B")), l2_width); + l2 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\B")), l2_width); ++line_num; str = stringf ("%d slice %d %d %d %d;6", line_num, extra_width, l2, l2_width-1, l2_width-extra_width); fprintf(f, "%s\n", str.c_str()); @@ -592,8 +592,8 @@ struct BtorDumper log("writing binary cell - %s\n", cstr(cell->type)); int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int(); log_assert(output_width == 1); - int l1 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\A")), output_width); - int l2 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\B")), output_width); + int l1 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\A")), output_width); + int l2 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\B")), output_width); int l1_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int(); int l2_width = cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int(); if(l1_width >1) @@ -628,9 +628,9 @@ struct BtorDumper { log("writing mux cell\n"); int output_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int(); - int l1 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\A")), output_width); - int l2 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\B")), output_width); - int s = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\S")), 1); + int l1 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\A")), output_width); + int l2 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\B")), output_width); + int s = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\S")), 1); ++line_num; str = stringf ("%d %s %d %d %d %d", line_num, cell_type_translation.at(cell->type).c_str(), output_width, s, l2, l1);//if s is 0 then l1, if s is 1 then l2 //according to the implementation of mux cell @@ -644,10 +644,10 @@ struct BtorDumper log("writing cell - %s\n", cstr(cell->type)); int output_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int(); log(" - width is %d\n", output_width); - int cond = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\CLK")), 1); + int cond = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\CLK")), 1); bool polarity = cell->parameters.at(RTLIL::IdString("\\CLK_POLARITY")).as_bool(); - const RTLIL::SigSpec* cell_output = &cell->connections_.at(RTLIL::IdString("\\Q")); - int value = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\D")), output_width); + const RTLIL::SigSpec* cell_output = &cell->connections().at(RTLIL::IdString("\\Q")); + int value = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\D")), output_width); unsigned start_bit = 0; for(unsigned i=0; ichunks().size(); ++i) { @@ -665,9 +665,9 @@ struct BtorDumper } if(cell->type == "$dffsr") { - int sync_reset = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\CLR")), 1); + int sync_reset = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\CLR")), 1); bool sync_reset_pol = cell->parameters.at(RTLIL::IdString("\\CLR_POLARITY")).as_bool(); - int sync_reset_value = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\SET")), + int sync_reset_value = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\SET")), output_width); bool sync_reset_value_pol = cell->parameters.at(RTLIL::IdString("\\SET_POLARITY")).as_bool(); ++line_num; @@ -685,7 +685,7 @@ struct BtorDumper int next = line_num; if(cell->type == "$adff") { - int async_reset = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\ARST")), 1); + int async_reset = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\ARST")), 1); bool async_reset_pol = cell->parameters.at(RTLIL::IdString("\\ARST_POLARITY")).as_bool(); int async_reset_value = dump_const(&cell->parameters.at(RTLIL::IdString("\\ARST_VALUE")), output_width, 0); @@ -710,7 +710,7 @@ struct BtorDumper str = cell->parameters.at(RTLIL::IdString("\\MEMID")).decode_string(); int mem = dump_memory(module->memories.at(RTLIL::IdString(str.c_str()))); int address_width = cell->parameters.at(RTLIL::IdString("\\ABITS")).as_int(); - int address = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\ADDR")), address_width); + int address = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\ADDR")), address_width); int data_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int(); ++line_num; str = stringf("%d read %d %d %d", line_num, data_width, mem, address); @@ -722,13 +722,13 @@ struct BtorDumper log("writing memwr cell\n"); if (cell->parameters.at("\\CLK_ENABLE").as_bool() == false) log_error("The btor backen does not support $memwr cells without built-in registers. Run memory_dff (but with -wr_only).\n"); - int clk = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\CLK")), 1); + int clk = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\CLK")), 1); bool polarity = cell->parameters.at(RTLIL::IdString("\\CLK_POLARITY")).as_bool(); - int enable = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\EN")), 1); + int enable = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\EN")), 1); int address_width = cell->parameters.at(RTLIL::IdString("\\ABITS")).as_int(); - int address = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\ADDR")), address_width); + int address = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\ADDR")), address_width); int data_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int(); - int data = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\DATA")), data_width); + int data = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\DATA")), data_width); str = cell->parameters.at(RTLIL::IdString("\\MEMID")).decode_string(); int mem = dump_memory(module->memories.at(RTLIL::IdString(str.c_str()))); ++line_num; @@ -757,11 +757,11 @@ struct BtorDumper else if(cell->type == "$slice") { log("writing slice cell\n"); - const RTLIL::SigSpec* input = &cell->connections_.at(RTLIL::IdString("\\A")); + const RTLIL::SigSpec* input = &cell->connections().at(RTLIL::IdString("\\A")); int input_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int(); log_assert(input->size() == input_width); int input_line = dump_sigspec(input, input_width); - const RTLIL::SigSpec* output = &cell->connections_.at(RTLIL::IdString("\\Y")); + const RTLIL::SigSpec* output = &cell->connections().at(RTLIL::IdString("\\Y")); int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int(); log_assert(output->size() == output_width); int offset = cell->parameters.at(RTLIL::IdString("\\OFFSET")).as_int(); @@ -773,11 +773,11 @@ struct BtorDumper else if(cell->type == "$concat") { log("writing concat cell\n"); - const RTLIL::SigSpec* input_a = &cell->connections_.at(RTLIL::IdString("\\A")); + const RTLIL::SigSpec* input_a = &cell->connections().at(RTLIL::IdString("\\A")); int input_a_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int(); log_assert(input_a->size() == input_a_width); int input_a_line = dump_sigspec(input_a, input_a_width); - const RTLIL::SigSpec* input_b = &cell->connections_.at(RTLIL::IdString("\\B")); + const RTLIL::SigSpec* input_b = &cell->connections().at(RTLIL::IdString("\\B")); int input_b_width = cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int(); log_assert(input_b->size() == input_b_width); int input_b_line = dump_sigspec(input_b, input_b_width); @@ -801,7 +801,7 @@ struct BtorDumper RTLIL::SigSpec *output_sig = nullptr; if (cell->type == "$memrd") { - output_sig = &cell->connections_.at(RTLIL::IdString("\\DATA")); + output_sig = &cell->connections().at(RTLIL::IdString("\\DATA")); } else if(cell->type == "$memwr" || cell->type == "$assert") { @@ -809,11 +809,11 @@ struct BtorDumper } else if(cell->type == "$dff" || cell->type == "$adff" || cell->type == "$dffsr") { - output_sig = &cell->connections_.at(RTLIL::IdString("\\Q")); + output_sig = &cell->connections().at(RTLIL::IdString("\\Q")); } else { - output_sig = &cell->connections_.at(RTLIL::IdString("\\Y")); + output_sig = &cell->connections().at(RTLIL::IdString("\\Y")); } return output_sig; } diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index 13ab4dc6..fc2f4a7e 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -148,7 +148,7 @@ struct EdifBackend : public Backend { RTLIL::Cell *cell = cell_it.second; if (!design->modules.count(cell->type) || design->modules.at(cell->type)->get_bool_attribute("\\blackbox")) { lib_cell_ports[cell->type]; - for (auto p : cell->connections_) { + for (auto p : cell->connections()) { if (p.second.size() > 1) log_error("Found multi-bit port %s on library cell %s.%s (%s): not supported in EDIF backend!\n", RTLIL::id2cstr(p.first), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); @@ -304,7 +304,7 @@ struct EdifBackend : public Backend { fprintf(f, "\n (property %s (string \"%s\"))", EDIF_DEF(p.first), hex_string.c_str()); } fprintf(f, ")\n"); - for (auto &p : cell->connections_) { + for (auto &p : cell->connections()) { RTLIL::SigSpec sig = sigmap(p.second); for (int i = 0; i < SIZE(sig); i++) if (sig.size() == 1) diff --git a/backends/ilang/ilang_backend.cc b/backends/ilang/ilang_backend.cc index 0e329fc9..6678f19d 100644 --- a/backends/ilang/ilang_backend.cc +++ b/backends/ilang/ilang_backend.cc @@ -163,7 +163,7 @@ void ILANG_BACKEND::dump_cell(FILE *f, std::string indent, const RTLIL::Cell *ce dump_const(f, it->second); fprintf(f, "\n"); } - for (auto it = cell->connections_.begin(); it != cell->connections_.end(); it++) { + for (auto it = cell->connections().begin(); it != cell->connections().end(); it++) { fprintf(f, "%s connect %s ", indent.c_str(), it->first.c_str()); dump_sigspec(f, it->second); fprintf(f, "\n"); @@ -309,7 +309,7 @@ void ILANG_BACKEND::dump_module(FILE *f, std::string indent, const RTLIL::Module } bool first_conn_line = true; - for (auto it = module->connections_.begin(); it != module->connections_.end(); it++) { + for (auto it = module->connections().begin(); it != module->connections().end(); it++) { bool show_conn = !only_selected; if (only_selected) { RTLIL::SigSpec sigs = it->first; diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index 8231f1d8..8c08747c 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -169,7 +169,7 @@ struct IntersynthBackend : public Backend { celltype_code = stringf("celltype %s", RTLIL::id2cstr(cell->type)); node_code = stringf("node %s %s", RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); - for (auto &port : cell->connections_) { + for (auto &port : cell->connections()) { RTLIL::SigSpec sig = sigmap(port.second); if (sig.size() != 0) { conntypes_code.insert(stringf("conntype b%d %d 2 %d\n", sig.size(), sig.size(), sig.size())); diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc index a3784f11..4bc8710e 100644 --- a/backends/spice/spice.cc +++ b/backends/spice/spice.cc @@ -58,7 +58,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de { log("Warning: no (blackbox) module for cell type `%s' (%s.%s) found! Guessing order of ports.\n", RTLIL::id2cstr(cell->type), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name)); - for (auto &conn : cell->connections_) { + for (auto &conn : cell->connections()) { RTLIL::SigSpec sig = sigmap(conn.second); port_sigs.push_back(sig); } @@ -80,8 +80,8 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de for (RTLIL::Wire *wire : ports) { log_assert(wire != NULL); RTLIL::SigSpec sig(RTLIL::State::Sz, wire->width); - if (cell->connections_.count(wire->name) > 0) { - sig = sigmap(cell->connections_.at(wire->name)); + if (cell->connections().count(wire->name) > 0) { + sig = sigmap(cell->connections().at(wire->name)); sig.extend(wire->width, false); } port_sigs.push_back(sig); @@ -98,7 +98,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de fprintf(f, " %s\n", RTLIL::id2cstr(cell->type)); } - for (auto &conn : module->connections_) + for (auto &conn : module->connections()) for (int i = 0; i < conn.first.size(); i++) { fprintf(f, "V%d", conn_counter++); print_spice_net(f, conn.first.extract(i, 1), neg, pos, ncpf, nc_counter); diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index d3b5d52d..aa2f88fa 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -293,17 +293,17 @@ void dump_cell_expr_port(FILE *f, RTLIL::Cell *cell, std::string port, bool gen_ { if (gen_signed && cell->parameters.count("\\" + port + "_SIGNED") > 0 && cell->parameters["\\" + port + "_SIGNED"].as_bool()) { fprintf(f, "$signed("); - dump_sigspec(f, cell->connections_["\\" + port]); + dump_sigspec(f, cell->connections()["\\" + port]); fprintf(f, ")"); } else - dump_sigspec(f, cell->connections_["\\" + port]); + dump_sigspec(f, cell->connections()["\\" + port]); } std::string cellname(RTLIL::Cell *cell) { - if (!norename && cell->name[0] == '$' && reg_ct.cell_known(cell->type) && cell->connections_.count("\\Q") > 0) + if (!norename && cell->name[0] == '$' && reg_ct.cell_known(cell->type) && cell->connections().count("\\Q") > 0) { - RTLIL::SigSpec sig = cell->connections_["\\Q"]; + RTLIL::SigSpec sig = cell->get("\\Q"); if (SIZE(sig) != 1 || sig.is_fully_const()) goto no_special_reg_name; @@ -338,7 +338,7 @@ no_special_reg_name: void dump_cell_expr_uniop(FILE *f, std::string indent, RTLIL::Cell *cell, std::string op) { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections_["\\Y"]); + dump_sigspec(f, cell->get("\\Y")); fprintf(f, " = %s ", op.c_str()); dump_attributes(f, "", cell->attributes, ' '); dump_cell_expr_port(f, cell, "A", true); @@ -348,7 +348,7 @@ void dump_cell_expr_uniop(FILE *f, std::string indent, RTLIL::Cell *cell, std::s void dump_cell_expr_binop(FILE *f, std::string indent, RTLIL::Cell *cell, std::string op) { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections_["\\Y"]); + dump_sigspec(f, cell->get("\\Y")); fprintf(f, " = "); dump_cell_expr_port(f, cell, "A", true); fprintf(f, " %s ", op.c_str()); @@ -361,7 +361,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) { if (cell->type == "$_INV_") { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections_["\\Y"]); + dump_sigspec(f, cell->get("\\Y")); fprintf(f, " = "); fprintf(f, "~"); dump_attributes(f, "", cell->attributes, ' '); @@ -372,7 +372,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$_AND_" || cell->type == "$_OR_" || cell->type == "$_XOR_") { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections_["\\Y"]); + dump_sigspec(f, cell->get("\\Y")); fprintf(f, " = "); dump_cell_expr_port(f, cell, "A", false); fprintf(f, " "); @@ -391,7 +391,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$_MUX_") { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections_["\\Y"]); + dump_sigspec(f, cell->get("\\Y")); fprintf(f, " = "); dump_cell_expr_port(f, cell, "S", false); fprintf(f, " ? "); @@ -406,23 +406,23 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (cell->type.substr(0, 6) == "$_DFF_") { std::string reg_name = cellname(cell); - bool out_is_reg_wire = is_reg_wire(cell->connections_["\\Q"], reg_name); + bool out_is_reg_wire = is_reg_wire(cell->get("\\Q"), reg_name); if (!out_is_reg_wire) fprintf(f, "%s" "reg %s;\n", indent.c_str(), reg_name.c_str()); dump_attributes(f, indent, cell->attributes); fprintf(f, "%s" "always @(%sedge ", indent.c_str(), cell->type[6] == 'P' ? "pos" : "neg"); - dump_sigspec(f, cell->connections_["\\C"]); + dump_sigspec(f, cell->get("\\C")); if (cell->type[7] != '_') { fprintf(f, " or %sedge ", cell->type[7] == 'P' ? "pos" : "neg"); - dump_sigspec(f, cell->connections_["\\R"]); + dump_sigspec(f, cell->get("\\R")); } fprintf(f, ")\n"); if (cell->type[7] != '_') { fprintf(f, "%s" " if (%s", indent.c_str(), cell->type[7] == 'P' ? "" : "!"); - dump_sigspec(f, cell->connections_["\\R"]); + dump_sigspec(f, cell->get("\\R")); fprintf(f, ")\n"); fprintf(f, "%s" " %s <= %c;\n", indent.c_str(), reg_name.c_str(), cell->type[8]); fprintf(f, "%s" " else\n", indent.c_str()); @@ -434,7 +434,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (!out_is_reg_wire) { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections_["\\Q"]); + dump_sigspec(f, cell->get("\\Q")); fprintf(f, " = %s;\n", reg_name.c_str()); } @@ -446,27 +446,27 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) char pol_c = cell->type[8], pol_s = cell->type[9], pol_r = cell->type[10]; std::string reg_name = cellname(cell); - bool out_is_reg_wire = is_reg_wire(cell->connections_["\\Q"], reg_name); + bool out_is_reg_wire = is_reg_wire(cell->get("\\Q"), reg_name); if (!out_is_reg_wire) fprintf(f, "%s" "reg %s;\n", indent.c_str(), reg_name.c_str()); dump_attributes(f, indent, cell->attributes); fprintf(f, "%s" "always @(%sedge ", indent.c_str(), pol_c == 'P' ? "pos" : "neg"); - dump_sigspec(f, cell->connections_["\\C"]); + dump_sigspec(f, cell->get("\\C")); fprintf(f, " or %sedge ", pol_s == 'P' ? "pos" : "neg"); - dump_sigspec(f, cell->connections_["\\S"]); + dump_sigspec(f, cell->get("\\S")); fprintf(f, " or %sedge ", pol_r == 'P' ? "pos" : "neg"); - dump_sigspec(f, cell->connections_["\\R"]); + dump_sigspec(f, cell->get("\\R")); fprintf(f, ")\n"); fprintf(f, "%s" " if (%s", indent.c_str(), pol_r == 'P' ? "" : "!"); - dump_sigspec(f, cell->connections_["\\R"]); + dump_sigspec(f, cell->get("\\R")); fprintf(f, ")\n"); fprintf(f, "%s" " %s <= 0;\n", indent.c_str(), reg_name.c_str()); fprintf(f, "%s" " else if (%s", indent.c_str(), pol_s == 'P' ? "" : "!"); - dump_sigspec(f, cell->connections_["\\S"]); + dump_sigspec(f, cell->get("\\S")); fprintf(f, ")\n"); fprintf(f, "%s" " %s <= 1;\n", indent.c_str(), reg_name.c_str()); @@ -477,7 +477,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (!out_is_reg_wire) { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections_["\\Q"]); + dump_sigspec(f, cell->get("\\Q")); fprintf(f, " = %s;\n", reg_name.c_str()); } @@ -535,7 +535,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$pmux_safe") { int width = cell->parameters["\\WIDTH"].as_int(); - int s_width = cell->connections_["\\S"].size(); + int s_width = cell->get("\\S").size(); std::string func_name = cellname(cell); fprintf(f, "%s" "function [%d:0] %s;\n", indent.c_str(), width-1, func_name.c_str()); @@ -567,13 +567,13 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) fprintf(f, "%s" "endfunction\n", indent.c_str()); fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections_["\\Y"]); + dump_sigspec(f, cell->get("\\Y")); fprintf(f, " = %s(", func_name.c_str()); - dump_sigspec(f, cell->connections_["\\A"]); + dump_sigspec(f, cell->get("\\A")); fprintf(f, ", "); - dump_sigspec(f, cell->connections_["\\B"]); + dump_sigspec(f, cell->get("\\B")); fprintf(f, ", "); - dump_sigspec(f, cell->connections_["\\S"]); + dump_sigspec(f, cell->get("\\S")); fprintf(f, ");\n"); return true; } @@ -581,9 +581,9 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$slice") { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections_["\\Y"]); + dump_sigspec(f, cell->get("\\Y")); fprintf(f, " = "); - dump_sigspec(f, cell->connections_["\\A"]); + dump_sigspec(f, cell->get("\\A")); fprintf(f, " >> %d;\n", cell->parameters.at("\\OFFSET").as_int()); return true; } @@ -591,14 +591,14 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$bu0") { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections_["\\Y"]); + dump_sigspec(f, cell->get("\\Y")); if (cell->parameters["\\A_SIGNED"].as_bool()) { fprintf(f, " = $signed("); - dump_sigspec(f, cell->connections_["\\A"]); + dump_sigspec(f, cell->get("\\A")); fprintf(f, ");\n"); } else { fprintf(f, " = { 1'b0, "); - dump_sigspec(f, cell->connections_["\\A"]); + dump_sigspec(f, cell->get("\\A")); fprintf(f, " };\n"); } return true; @@ -607,11 +607,11 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$concat") { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections_["\\Y"]); + dump_sigspec(f, cell->get("\\Y")); fprintf(f, " = { "); - dump_sigspec(f, cell->connections_["\\B"]); + dump_sigspec(f, cell->get("\\B")); fprintf(f, " , "); - dump_sigspec(f, cell->connections_["\\A"]); + dump_sigspec(f, cell->get("\\A")); fprintf(f, " };\n"); return true; } @@ -621,17 +621,17 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) RTLIL::SigSpec sig_clk, sig_arst, val_arst; bool pol_clk, pol_arst = false; - sig_clk = cell->connections_["\\CLK"]; + sig_clk = cell->get("\\CLK"); pol_clk = cell->parameters["\\CLK_POLARITY"].as_bool(); if (cell->type == "$adff") { - sig_arst = cell->connections_["\\ARST"]; + sig_arst = cell->get("\\ARST"); pol_arst = cell->parameters["\\ARST_POLARITY"].as_bool(); val_arst = RTLIL::SigSpec(cell->parameters["\\ARST_VALUE"]); } std::string reg_name = cellname(cell); - bool out_is_reg_wire = is_reg_wire(cell->connections_["\\Q"], reg_name); + bool out_is_reg_wire = is_reg_wire(cell->get("\\Q"), reg_name); if (!out_is_reg_wire) fprintf(f, "%s" "reg [%d:0] %s;\n", indent.c_str(), cell->parameters["\\WIDTH"].as_int()-1, reg_name.c_str()); @@ -660,7 +660,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (!out_is_reg_wire) { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections_["\\Q"]); + dump_sigspec(f, cell->get("\\Q")); fprintf(f, " = %s;\n", reg_name.c_str()); } @@ -707,7 +707,7 @@ void dump_cell(FILE *f, std::string indent, RTLIL::Cell *cell) for (int i = 1; true; i++) { char str[16]; snprintf(str, 16, "$%d", i); - for (auto it = cell->connections_.begin(); it != cell->connections_.end(); it++) { + for (auto it = cell->connections().begin(); it != cell->connections().end(); it++) { if (it->first != str) continue; if (!first_arg) @@ -721,7 +721,7 @@ void dump_cell(FILE *f, std::string indent, RTLIL::Cell *cell) break; found_numbered_port:; } - for (auto it = cell->connections_.begin(); it != cell->connections_.end(); it++) { + for (auto it = cell->connections().begin(); it != cell->connections().end(); it++) { if (numbered_ports.count(it->first)) continue; if (!first_arg) @@ -908,10 +908,10 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module) for (auto &it : module->cells) { RTLIL::Cell *cell = it.second; - if (!reg_ct.cell_known(cell->type) || cell->connections_.count("\\Q") == 0) + if (!reg_ct.cell_known(cell->type) || cell->connections().count("\\Q") == 0) continue; - RTLIL::SigSpec sig = cell->connections_["\\Q"]; + RTLIL::SigSpec sig = cell->get("\\Q"); if (sig.is_chunk()) { RTLIL::SigChunk chunk = sig.as_chunk(); @@ -961,7 +961,7 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module) for (auto it = module->processes.begin(); it != module->processes.end(); it++) dump_process(f, indent + " ", it->second); - for (auto it = module->connections_.begin(); it != module->connections_.end(); it++) + for (auto it = module->connections().begin(); it != module->connections().end(); it++) dump_conn(f, indent + " ", it->first, it->second); fprintf(f, "%s" "endmodule\n", indent.c_str()); -- cgit v1.2.3 From f8fdc47d3361c1a3445a9357ca26cfe75907d6b0 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 15:57:57 +0200 Subject: Manual fixes for new cell connections API --- backends/btor/btor.cc | 8 ++++---- backends/verilog/verilog_backend.cc | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) (limited to 'backends') diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc index 0316f7ab..bbfbc0f9 100644 --- a/backends/btor/btor.cc +++ b/backends/btor/btor.cc @@ -193,7 +193,7 @@ struct BtorDumper break; log(" -- found cell %s\n", cstr(cell_id)); RTLIL::Cell* cell = module->cells.at(cell_id); - RTLIL::SigSpec* cell_output = get_cell_output(cell); + const RTLIL::SigSpec* cell_output = get_cell_output(cell); int cell_line = dump_cell(cell); if(dep_set.size()==1 && wire->width == cell_output->size()) @@ -796,9 +796,9 @@ struct BtorDumper } } - RTLIL::SigSpec* get_cell_output(RTLIL::Cell* cell) + const RTLIL::SigSpec* get_cell_output(RTLIL::Cell* cell) { - RTLIL::SigSpec *output_sig = nullptr; + const RTLIL::SigSpec *output_sig = nullptr; if (cell->type == "$memrd") { output_sig = &cell->connections().at(RTLIL::IdString("\\DATA")); @@ -835,7 +835,7 @@ struct BtorDumper for (auto it = module->cells.begin(); it != module->cells.end(); ++it) { RTLIL::Cell *cell = it->second; - RTLIL::SigSpec* output_sig = get_cell_output(cell); + const RTLIL::SigSpec* output_sig = get_cell_output(cell); if(output_sig==nullptr) continue; RTLIL::SigSpec s = sigmap(*output_sig); diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index aa2f88fa..6bef90e3 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -223,7 +223,7 @@ void dump_sigchunk(FILE *f, const RTLIL::SigChunk &chunk, bool no_decimal = fals } } -void dump_sigspec(FILE *f, RTLIL::SigSpec &sig) +void dump_sigspec(FILE *f, const RTLIL::SigSpec &sig) { if (sig.is_chunk()) { dump_sigchunk(f, sig.as_chunk()); @@ -293,10 +293,10 @@ void dump_cell_expr_port(FILE *f, RTLIL::Cell *cell, std::string port, bool gen_ { if (gen_signed && cell->parameters.count("\\" + port + "_SIGNED") > 0 && cell->parameters["\\" + port + "_SIGNED"].as_bool()) { fprintf(f, "$signed("); - dump_sigspec(f, cell->connections()["\\" + port]); + dump_sigspec(f, cell->get("\\" + port)); fprintf(f, ")"); } else - dump_sigspec(f, cell->connections()["\\" + port]); + dump_sigspec(f, cell->get("\\" + port)); } std::string cellname(RTLIL::Cell *cell) @@ -735,7 +735,7 @@ void dump_cell(FILE *f, std::string indent, RTLIL::Cell *cell) fprintf(f, "\n%s" ");\n", indent.c_str()); } -void dump_conn(FILE *f, std::string indent, RTLIL::SigSpec &left, RTLIL::SigSpec &right) +void dump_conn(FILE *f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right) { fprintf(f, "%s" "assign ", indent.c_str()); dump_sigspec(f, left); -- cgit v1.2.3