From b0c0ede879341c0beeae4a9a5e8578da12f3b3f1 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 4 Apr 2015 18:06:52 +0200 Subject: Added "init" attribute support to verilog backend --- backends/verilog/verilog_backend.cc | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'backends') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index ba57e881..0d667c63 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -299,6 +299,11 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire) f << stringf("%s" "reg%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str()); else if (!wire->port_input && !wire->port_output) f << stringf("%s" "wire%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str()); + if (wire->attributes.count("\\init")) { + f << stringf("%s" "initial %s = ", indent.c_str(), id(wire->name).c_str()); + dump_const(f, wire->attributes.at("\\init")); + f << stringf(";\n"); + } #endif } -- cgit v1.2.3