From ca1b5d50e0e577a88ae265b71679b81e71980db8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 2 Aug 2014 21:10:08 +0200 Subject: Improved verilog output for ordinary $mux cells --- backends/verilog/verilog_backend.cc | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) (limited to 'backends') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index e3c930c8..c691eae6 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -544,7 +544,22 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) #undef HANDLE_UNIOP #undef HANDLE_BINOP - if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$pmux_safe") + if (cell->type == "$mux") + { + fprintf(f, "%s" "assign ", indent.c_str()); + dump_sigspec(f, cell->getPort("\\Y")); + fprintf(f, " = "); + dump_sigspec(f, cell->getPort("\\S")); + fprintf(f, " ? "); + dump_attributes(f, "", cell->attributes, ' '); + dump_sigspec(f, cell->getPort("\\B")); + fprintf(f, " : "); + dump_sigspec(f, cell->getPort("\\A")); + fprintf(f, ";\n"); + return true; + } + + if (cell->type == "$pmux" || cell->type == "$pmux_safe") { int width = cell->parameters["\\WIDTH"].as_int(); int s_width = cell->getPort("\\S").size(); @@ -556,10 +571,11 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) fprintf(f, "%s" " input [%d:0] s;\n", indent.c_str(), s_width-1); dump_attributes(f, indent + " ", cell->attributes); - if (!noattr) + if (cell->type != "$pmux_safe" && !noattr) fprintf(f, "%s" " (* parallel_case *)\n", indent.c_str()); fprintf(f, "%s" " casez (s)", indent.c_str()); - fprintf(f, noattr ? " // synopsys parallel_case\n" : "\n"); + if (cell->type != "$pmux_safe") + fprintf(f, noattr ? " // synopsys parallel_case\n" : "\n"); for (int i = 0; i < s_width; i++) { -- cgit v1.2.3