From e0f693cbb09ac1a952fc49e507daefa30169bd35 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 18 Oct 2013 12:13:34 +0200 Subject: Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_ --- backends/verilog/verilog_backend.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'backends') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index e0794ad6..d64deb64 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -573,6 +573,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) return true; } + // FIXME: $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_ // FIXME: $sr, $dffsr, $dlatch, $memrd, $memwr, $mem, $fsm return false; -- cgit v1.2.3