From f9a307a50b5ce67b67d2b53e8c1334ea23ffd997 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 27 Sep 2014 16:17:53 +0200 Subject: namespace Yosys --- backends/blif/blif.cc | 4 ++++ backends/btor/btor.cc | 4 ++++ backends/edif/edif.cc | 4 ++++ backends/ilang/ilang_backend.cc | 6 ++++++ backends/intersynth/intersynth.cc | 3 +++ backends/spice/spice.cc | 4 ++++ backends/verilog/verilog_backend.cc | 7 +++---- backends/verilog/verilog_backend.h | 38 ------------------------------------- 8 files changed, 28 insertions(+), 42 deletions(-) delete mode 100644 backends/verilog/verilog_backend.h (limited to 'backends') diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc index ee12546c..216e59fb 100644 --- a/backends/blif/blif.cc +++ b/backends/blif/blif.cc @@ -28,6 +28,9 @@ #include "kernel/log.h" #include +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + struct BlifDumperConfig { bool icells_mode; @@ -397,3 +400,4 @@ struct BlifBackend : public Backend { } } BlifBackend; +PRIVATE_NAMESPACE_END diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc index 8ce5bb5e..5bd71716 100644 --- a/backends/btor/btor.cc +++ b/backends/btor/btor.cc @@ -30,6 +30,9 @@ #include #include +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + struct BtorDumperConfig { bool subckt_mode; @@ -1057,3 +1060,4 @@ struct BtorBackend : public Backend { } } BtorBackend; +PRIVATE_NAMESPACE_END diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index ccedd91d..7f29cd41 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -27,6 +27,9 @@ #include "kernel/log.h" #include +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + #define EDIF_DEF(_id) edif_names(RTLIL::unescape_id(_id), true).c_str() #define EDIF_REF(_id) edif_names(RTLIL::unescape_id(_id), false).c_str() @@ -345,3 +348,4 @@ struct EdifBackend : public Backend { } } EdifBackend; +PRIVATE_NAMESPACE_END diff --git a/backends/ilang/ilang_backend.cc b/backends/ilang/ilang_backend.cc index 48d818d7..19c2805c 100644 --- a/backends/ilang/ilang_backend.cc +++ b/backends/ilang/ilang_backend.cc @@ -26,7 +26,9 @@ #include "kernel/yosys.h" #include +USING_YOSYS_NAMESPACE using namespace ILANG_BACKEND; +YOSYS_NAMESPACE_BEGIN void ILANG_BACKEND::dump_const(std::ostream &f, const RTLIL::Const &data, int width, int offset, bool autoint) { @@ -391,6 +393,9 @@ void ILANG_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool onl log_assert(init_autoidx == autoidx); } +YOSYS_NAMESPACE_END +PRIVATE_NAMESPACE_BEGIN + struct IlangBackend : public Backend { IlangBackend() : Backend("ilang", "write design to ilang file") { } virtual void help() @@ -510,3 +515,4 @@ struct DumpPass : public Pass { } } DumpPass; +PRIVATE_NAMESPACE_END diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index 8502d90f..6d4731e7 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -24,6 +24,8 @@ #include "kernel/log.h" #include +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN static std::string netname(std::set &conntypes_code, std::set &celltypes_code, std::set &constcells_code, RTLIL::SigSpec sig) { @@ -215,3 +217,4 @@ struct IntersynthBackend : public Backend { } } IntersynthBackend; +PRIVATE_NAMESPACE_END diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc index b057063c..2aff9419 100644 --- a/backends/spice/spice.cc +++ b/backends/spice/spice.cc @@ -24,6 +24,9 @@ #include "kernel/log.h" #include +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + static void print_spice_net(std::ostream &f, RTLIL::SigBit s, std::string &neg, std::string &pos, std::string &ncpf, int &nc_counter) { if (s.wire) { @@ -231,3 +234,4 @@ struct SpiceBackend : public Backend { } } SpiceBackend; +PRIVATE_NAMESPACE_END diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index bbdbbbfa..99430d04 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -26,7 +26,6 @@ * */ -#include "verilog_backend.h" #include "kernel/register.h" #include "kernel/celltypes.h" #include "kernel/log.h" @@ -35,7 +34,8 @@ #include #include -namespace { +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN bool norename, noattr, attr2comment, noexpr; int auto_name_counter, auto_name_offset, auto_name_digits; @@ -1016,8 +1016,6 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) active_module = NULL; } -} /* namespace */ - struct VerilogBackend : public Backend { VerilogBackend() : Backend("verilog", "write design to verilog file") { } virtual void help() @@ -1139,3 +1137,4 @@ struct VerilogBackend : public Backend { } } VerilogBackend; +PRIVATE_NAMESPACE_END diff --git a/backends/verilog/verilog_backend.h b/backends/verilog/verilog_backend.h deleted file mode 100644 index 7e6ef5ab..00000000 --- a/backends/verilog/verilog_backend.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - * --- - * - * A simple and straightforward verilog backend. - * - * Note that RTLIL processes can't always be mapped easily to a Verilog - * process. Therefore this frontend should only be used to export a - * Verilog netlist (i.e. after the "proc" pass has converted all processes - * to logic networks and registers). - * - */ - -#ifndef VERILOG_BACKEND_H -#define VERILOG_BACKEND_H - -#include "kernel/yosys.h" - -namespace VERILOG_BACKEND { - void verilog_backend(std::ostream &f, std::vector args, RTLIL::Design *design); -} - -#endif -- cgit v1.2.3