From 9dd16fa41c01c8da2e4905184cce0391a7547fa3 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 14 Jun 2014 07:44:19 +0200 Subject: Added real->int convertion in ast genrtlil --- frontends/ast/genrtlil.cc | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'frontends/ast') diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 9273636f..5b43f57f 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -602,6 +602,10 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint) sign_hint = false; break; + case AST_REALVALUE: + width_hint = std::max(width_hint, 32); + break; + case AST_IDENTIFIER: id_ast = id2ast; if (id_ast == NULL && current_scope.count(str)) @@ -909,6 +913,14 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) return RTLIL::SigSpec(bitsAsConst()); } + case AST_REALVALUE: + { + int intvalue = round(realvalue); + log("Warning: converting real value %e to integer %d at %s:%d.\n", + realvalue, intvalue, filename.c_str(), linenum); + return RTLIL::SigSpec(intvalue); + } + // simply return the corresponding RTLIL::SigSpec for an AST_IDENTIFIER node // for identifiers with dynamic bit ranges (e.g. "foo[bar]" or "foo[bar+3:bar]") a // shifter cell is created and the output signal of this cell is returned -- cgit v1.2.3