From 4c4b6021562c598c4510831bd547edaa97d14dac Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 01:51:45 +0200 Subject: Refactoring: Renamed RTLIL::Module::cells to cells_ --- frontends/liberty/liberty.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'frontends/liberty') diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc index c476de87..0107b974 100644 --- a/frontends/liberty/liberty.cc +++ b/frontends/liberty/liberty.cc @@ -239,7 +239,7 @@ static void create_ff(RTLIL::Module *module, LibertyAst *node) { rerun_invert_rollback = false; - for (auto &it : module->cells) { + for (auto &it : module->cells_) { if (it.second->type == "$_INV_" && it.second->get("\\Y") == clk_sig) { clk_sig = it.second->get("\\A"); clk_polarity = !clk_polarity; @@ -316,7 +316,7 @@ static void create_latch(RTLIL::Module *module, LibertyAst *node) { rerun_invert_rollback = false; - for (auto &it : module->cells) { + for (auto &it : module->cells_) { if (it.second->type == "$_INV_" && it.second->get("\\Y") == enable_sig) { enable_sig = it.second->get("\\A"); enable_polarity = !enable_polarity; -- cgit v1.2.3