From 924d9d6e86a5e9a2294479345daac1c03d78008a Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 25 Sep 2015 12:23:11 +0200
Subject: Added read-enable to memory model

---
 frontends/verific/verific.cc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'frontends/verific/verific.cc')

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 897a7f32..793c0684 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -692,7 +692,8 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
 			cell->parameters["\\TRANSPARENT"] = false;
 			cell->parameters["\\ABITS"] = GetSize(addr);
 			cell->parameters["\\WIDTH"] = GetSize(data);
-			cell->setPort("\\CLK", RTLIL::State::S0);
+			cell->setPort("\\CLK", RTLIL::State::Sx);
+			cell->setPort("\\EN", RTLIL::State::Sx);
 			cell->setPort("\\ADDR", addr);
 			cell->setPort("\\DATA", data);
 			continue;
-- 
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