From 00a6c1d9a57da0e0b0fef07b2d618847ed93a9fd Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 9 Jul 2013 14:31:57 +0200
Subject: Major redesign of expr width/sign detecion (verilog/ast frontend)

---
 frontends/verilog/const2ast.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'frontends/verilog/const2ast.cc')

diff --git a/frontends/verilog/const2ast.cc b/frontends/verilog/const2ast.cc
index 3a88fc04..e38ff204 100644
--- a/frontends/verilog/const2ast.cc
+++ b/frontends/verilog/const2ast.cc
@@ -161,7 +161,7 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type)
 	if (str == endptr)
 		intval = -1;
 
-	// The "<bits>'[bodh]<digits>" syntax
+	// The "<bits>'s?[bodh]<digits>" syntax
 	if (*endptr == '\'')
 	{
 		int len_in_bits = intval;
-- 
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