From 46fbe9d26299a7b6197463b3056d778f525658fb Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 7 Jun 2013 13:59:13 +0200 Subject: Added SAT generator and simple sat_solve command --- frontends/verilog/const2ast.cc | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'frontends/verilog/const2ast.cc') diff --git a/frontends/verilog/const2ast.cc b/frontends/verilog/const2ast.cc index e5beaead..3a88fc04 100644 --- a/frontends/verilog/const2ast.cc +++ b/frontends/verilog/const2ast.cc @@ -186,12 +186,11 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type) my_strtobin(data, endptr+2, len_in_bits, 16, case_type); break; default: - goto error; + return NULL; } return AstNode::mkconst_bits(data, is_signed); } -error: - log_error("Value conversion failed: `%s'\n", code.c_str()); + return NULL; } -- cgit v1.2.3