From 161565be104fd0c7b7c4224bd23e9502625e041a Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 31 Mar 2013 11:19:11 +0200
Subject: Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)

---
 frontends/verilog/parser.y | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'frontends/verilog/parser.y')

diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y
index 9caa236f..22af178e 100644
--- a/frontends/verilog/parser.y
+++ b/frontends/verilog/parser.y
@@ -607,7 +607,7 @@ always_stmt:
 		ast_stack.pop_back();
 	} |
 	attr TOK_INITIAL {
-		AstNode *node = new AstNode(AST_ALWAYS);
+		AstNode *node = new AstNode(AST_INITIAL);
 		append_attr(node, $1);
 		ast_stack.back()->children.push_back(node);
 		ast_stack.push_back(node);
-- 
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