From 13359d65ba8cc4a968b5b27deef4040fb2430899 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 18 Jan 2014 19:22:20 +0100 Subject: Fixed parsing of verilog macros at end of line --- frontends/verilog/preproc.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'frontends/verilog/preproc.cc') diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc index 5cfa0f24..db53e8c6 100644 --- a/frontends/verilog/preproc.cc +++ b/frontends/verilog/preproc.cc @@ -386,7 +386,7 @@ std::string frontend_verilog_preproc(FILE *f, std::string filename, const std::m std::string name = tok.substr(1); // printf("expand: >>%s<< -> >>%s<<\n", name.c_str(), defines_map[name].c_str()); std::string skipped_spaces = skip_spaces(); - tok = next_token(true); + tok = next_token(false); if (tok == "(" && defines_with_args.count(name) > 0) { int level = 1; std::vector args; -- cgit v1.2.3