From 482d9208aa9dacb7afe21f08c882d4881581013a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 12 Jun 2014 11:54:20 +0200 Subject: Added read_verilog -sv options, added support for bit, logic, allways_ff, always_comb, and always_latch --- frontends/verilog/verilog_frontend.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'frontends/verilog/verilog_frontend.h') diff --git a/frontends/verilog/verilog_frontend.h b/frontends/verilog/verilog_frontend.h index 99b2164e..6d01a153 100644 --- a/frontends/verilog/verilog_frontend.h +++ b/frontends/verilog/verilog_frontend.h @@ -45,6 +45,9 @@ namespace VERILOG_FRONTEND // state of `default_nettype extern bool default_nettype_wire; + + // running in SystemVerilog mode + extern bool sv_mode; } // the pre-processor -- cgit v1.2.3