From 0c6ffc4c656de69c92727580cd4c192211d10e6d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 13 Jun 2013 11:18:45 +0200 Subject: More fixes for bugs found using xsthammer --- frontends/verilog/lexer.l | 4 ++-- frontends/verilog/parser.y | 14 ++++++++++++-- 2 files changed, 14 insertions(+), 4 deletions(-) (limited to 'frontends/verilog') diff --git a/frontends/verilog/lexer.l b/frontends/verilog/lexer.l index 783b790b..78f1d367 100644 --- a/frontends/verilog/lexer.l +++ b/frontends/verilog/lexer.l @@ -236,8 +236,8 @@ supply1 { return TOK_SUPPLY1; } "===" { return OP_EQ; } "!==" { return OP_NE; } - /* "~&" { return OP_NAND; } */ - /* "~|" { return OP_NOR; } */ +"~&" { return OP_NAND; } +"~|" { return OP_NOR; } "~^" { return OP_XNOR; } "^~" { return OP_XNOR; } diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y index ea39e83d..68ac26bf 100644 --- a/frontends/verilog/parser.y +++ b/frontends/verilog/parser.y @@ -113,9 +113,9 @@ static void free_attr(std::map *al) // operator precedence from low to high %left OP_LOR %left OP_LAND -%left '|' +%left '|' OP_NOR %left '^' OP_XNOR -%left '&' +%left '&' OP_NAND %left OP_EQ OP_NE %left '<' OP_LE OP_GE '>' %left OP_SHL OP_SHR OP_SSHL OP_SSHR @@ -982,10 +982,20 @@ basic_expr: $$ = new AstNode(AST_REDUCE_AND, $3); append_attr($$, $2); } | + OP_NAND attr basic_expr %prec UNARY_OPS { + $$ = new AstNode(AST_REDUCE_AND, $3); + append_attr($$, $2); + $$ = new AstNode(AST_LOGIC_NOT, $$); + } | '|' attr basic_expr %prec UNARY_OPS { $$ = new AstNode(AST_REDUCE_OR, $3); append_attr($$, $2); } | + OP_NOR attr basic_expr %prec UNARY_OPS { + $$ = new AstNode(AST_REDUCE_OR, $3); + append_attr($$, $2); + $$ = new AstNode(AST_LOGIC_NOT, $$); + } | '^' attr basic_expr %prec UNARY_OPS { $$ = new AstNode(AST_REDUCE_XOR, $3); append_attr($$, $2); -- cgit v1.2.3